{"id":7948,"date":"2026-06-28T06:01:48","date_gmt":"2026-06-28T06:01:48","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls10n\/"},"modified":"2026-06-28T11:45:26","modified_gmt":"2026-06-28T11:45:26","slug":"sn74ls10n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/sn74ls10n\/","title":{"rendered":"SN74LS10N"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The SN74LS10N from Texas Instruments is a triple 3-input positive NAND gate with LS TTL technology, 12ns propagation delay, and industry-standard 7410 pinout in a 14-pin PDIP package.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n3 (triple 3-input NAND)<\/td>\n<\/tr>\n
\u0639\u0627\u0626\u0644\u0629 \u0627\u0644\u0645\u0646\u0637\u0642<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n12ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n8mA \/ -0.4mA<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • Three independent 3-input NAND gates<\/li>\n
  • LS TTL technology<\/li>\n
  • 12ns typical propagation delay<\/li>\n
  • Industry-standard 7410 pinout<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • 3-input majority logic<\/li>\n
    • Active-low signal combination<\/li>\n
    • Address decoding<\/li>\n
    • General-purpose combinational logic<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS10N from Texas Instruments is a triple 3-input positive NAND gate with LS TTL technology, 12ns propagation delay, and industry-standard 7410 pinout in a 14-pin PDIP package. Key Specifications Number of Gates 3 (triple 3-input NAND) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Propagation Delay 12ns typical […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7948","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Triple 3-input NAND gate, LS TTL, 12ns, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls10.pdf","price":"$0.35 @ 1ku","product_introduction":"The SN74LS10N from Texas Instruments contains three independent 3-input NAND gates in a 14-pin PDIP package. Each gate performs Y = NOT(A AND B AND C); the output is LOW only when ALL three inputs are HIGH. The 3-input NAND is essential for majority logic and multi-condition gating where an action requires multiple conditions to be met simultaneously. Unlike the 2-input 7400, the 7410 tests for conjunction of three signals, useful in address decoding where three address lines must all be HIGH to select a particular memory range. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each 3-input NAND gate in the SN74LS10N performs Y = A NAND B NAND C = NOT(A AND B AND C). The truth table has 8 entries: the output is LOW only for the single case A=B=C=HIGH (111\u21920); for all other 7 input combinations, the output is HIGH. This makes the 3-input NAND a natural majority detector with inverted output: it detects when all three inputs agree (are HIGH). For an active-LOW AND (output goes LOW when all inputs are HIGH), the 3-input NAND is used directly. For a 3-input AND (output goes HIGH when all inputs are HIGH), add an inverter after the NAND, or use one gate of a 7404. For majority logic (output HIGH when 2 or more of 3 inputs are HIGH), a more complex circuit using multiple gates is needed.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      4<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      5<\/td>2C<\/td>Input<\/td>Gate 2 input C<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Gate 2 output (NAND)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Gate 3 output (NAND)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Gate 3 input A<\/td><\/tr>\n
      10<\/td>3B<\/td>Input<\/td>Gate 3 input B<\/td><\/tr>\n
      11<\/td>3C<\/td>Input<\/td>Gate 3 input C<\/td><\/tr>\n
      12<\/td>1Y<\/td>Output<\/td>Gate 1 output (NAND)<\/td><\/tr>\n
      13<\/td>1C<\/td>Input<\/td>Gate 1 input C<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 3-Condition Gate:<\/strong> Output LOW only when all 3 conditions (inputs) are HIGH; e.g., chip select = \/CS when A15=A14=A13=1<\/li>\n
      • 3-Input AND:<\/strong> NAND gate + inverter; Y = A AND B AND C; all three must be HIGH for HIGH output<\/li>\n
      • Address Decode:<\/strong> Three high-order address bits \u2192 3-input NAND; output LOW when specific address range selected<\/li>\n
      • Strobe Gate:<\/strong> Data signal on one input, two enable signals on others; output active only when both enables HIGH<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS10N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS10D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC10D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC10N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT10D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT10N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC10D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC10N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7410 is a Triple 3-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7948","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=7948"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7948\/revisions"}],"predecessor-version":[{"id":8177,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7948\/revisions\/8177"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=7948"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=7948"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=7948"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=7948"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}