{"id":7916,"date":"2026-06-28T04:21:30","date_gmt":"2026-06-28T04:21:30","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls32n\/"},"modified":"2026-06-28T11:46:08","modified_gmt":"2026-06-28T11:46:08","slug":"sn74ls32n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/sn74ls32n\/","title":{"rendered":"SN74LS32N"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The SN74LS32N is a quad 2-input OR gate from Texas Instruments with LS TTL technology, 14ns propagation delay, and industry-standard pinout in a 14-pin PDIP package.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n4 (quad 2-input OR)<\/td>\n<\/tr>\n
\u0639\u0627\u0626\u0644\u0629 \u0627\u0644\u0645\u0646\u0637\u0642<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n14ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n8mA \/ -0.4mA<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • Four independent 2-input OR gates<\/li>\n
  • LS TTL technology<\/li>\n
  • 14ns typical propagation delay<\/li>\n
  • Industry-standard 7432 pinout<\/li>\n
  • Input clamp diodes for undershoot protection<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Logic OR function implementation<\/li>\n
    • Interrupt signal combination<\/li>\n
    • Alarm and fault aggregation<\/li>\n
    • Address decoding logic<\/li>\n
    • General-purpose logic gating<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS32N is a quad 2-input OR gate from Texas Instruments with LS TTL technology, 14ns propagation delay, and industry-standard pinout in a 14-pin PDIP package. Key Specifications Number of Gates 4 (quad 2-input OR) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Propagation Delay 14ns typical @ 5V […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7916","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad 2-input OR gate, LS TTL, 14ns, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":12000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls32.pdf","price":"$0.30 @ 1ku","product_introduction":"The SN74LS32N from Texas Instruments contains four independent 2-input OR gates in a 14-pin PDIP through-hole package. Each gate performs the Boolean function Y = A OR B; the output is HIGH when either or both inputs are HIGH. The LS (Low-power Schottky) technology provides 14ns typical propagation delay with moderate power consumption. The device is one of the fundamental 7400-series logic ICs, useful for combining multiple active-HIGH signals into a single output. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each of the four OR gates in the SN74LS32N performs the Boolean function Y = A + B (inclusive OR). The output is LOW only when both inputs A and B are LOW; for all other input combinations (01, 10, 11), the output is HIGH. The LS TTL implementation uses diode-transistor logic for the input stage and a totem-pole output stage. The 14ns propagation delay means the output transitions approximately 14ns after the input changes. OR gates are commonly used to combine multiple interrupt request lines into a single interrupt input, where any source can trigger the interrupt. An OR gate can also be constructed from NAND gates (DeMorgan's theorem: A+B = NOT(NOT(A) \u00b7 NOT(B))), but the 7432 provides this function directly with fewer gates and lower delay.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>1Y<\/td>Output<\/td>Gate 1 output (OR)<\/td><\/tr>\n
      4<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      5<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Gate 2 output (OR)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Gate 3 output (OR)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Gate 3 input A<\/td><\/tr>\n
      10<\/td>3B<\/td>Input<\/td>Gate 3 input B<\/td><\/tr>\n
      11<\/td>4Y<\/td>Output<\/td>Gate 4 output (OR)<\/td><\/tr>\n
      12<\/td>4A<\/td>Input<\/td>Gate 4 input A<\/td><\/tr>\n
      13<\/td>4B<\/td>Input<\/td>Gate 4 input B<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Interrupt OR:<\/strong> Combine 2 active-HIGH interrupt lines into single MCU interrupt pin; any source triggers interrupt<\/li>\n
      • Alarm Aggregation:<\/strong> Multiple fault signals ORed into single alarm; Y=HIGH when any fault is active<\/li>\n
      • Address Decode:<\/strong> OR combines chip select from multiple address ranges into single peripheral enable<\/li>\n
      • Enable Logic:<\/strong> Either of two enable signals activates the output; A OR B = enable<\/li>\n
      • Signal Merge:<\/strong> Combine two clock or strobe signals where either one activates the next stage<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS32N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS32D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC32D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT32D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC32D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC32D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC32N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7432 is a Quad 2-Input OR Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7916","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=7916"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7916\/revisions"}],"predecessor-version":[{"id":8193,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7916\/revisions\/8193"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=7916"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=7916"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=7916"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=7916"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}