The TL16C752DPFBR from Texas Instruments is a dual UART with 64-byte FIFOs in a 48-pin TQFP package. Supporting data rates up to 3Mbps with automatic hardware\/software flow control, it provides two independent serial communication channels from a single IC.<\/p>\n
| \u0627\u0644\u0642\u0646\u0648\u0627\u062a<\/td>\n | 2 (dual UART)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| FIFO Depth<\/td>\n | 64 bytes TX and RX per channel<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Max Data Rate<\/td>\n | 3 Mbps (48MHz clock at 5V\/3.3V)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| \u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n | 1.62 V to 5.5 V<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| \u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n | -40C to +85C<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Flow Control<\/td>\n | Auto hardware (RTS\/CTS) and software (XON\/XOFF)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| \u0627\u0644\u0648\u0627\u062c\u0647\u0629<\/td>\n | Parallel data bus, 8-bit<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Modem Control<\/td>\n | CTS, RTS, DSR, DTR, RI, CD<\/td>\n<\/tr>\n<\/table>\n\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\nProduct Overview The TL16C752DPFBR from Texas Instruments is a dual UART with 64-byte FIFOs in a 48-pin TQFP package. Supporting data rates up to 3Mbps with automatic hardware\/software flow control, it provides two independent serial communication channels from a single IC. Key Specifications Channels 2 (dual UART) FIFO Depth 64 bytes TX and RX per […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7252","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual UART, 64-byte FIFO, 3Mbps, 1.62-5.5V, TQFP-48, auto flow control, IrDA, RS-485","date_code":"","package_case":"TQFP-48 (7.00 x 7.00 mm, PFB package)","in_stock":10689,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/sllsen8b\/sllsen8b.pdf","price":"$3.50 @ 1ku","product_introduction":"The TL16C752DPFBR from Texas Instruments is a dual universal asynchronous receiver\/transmitter (UART) with 64-byte transmit and receive FIFOs in a 48-pin TQFP package. The device incorporates two independent UART channels, each with its own register set and FIFOs, sharing only the parallel data bus interface and clock source. Each channel supports data rates up to 3Mbps with a 48MHz oscillator input clock at 5V or 3.3V supply. The wide 1.62V to 5.5V supply range supports mixed-voltage system designs. The 64-byte FIFOs with programmable trigger levels significantly reduce CPU interrupt overhead by allowing the processor to service larger data blocks. Automatic hardware flow control (auto-RTS and auto-CTS) and software flow control (programmable XON\/XOFF characters) prevent data overrun without CPU intervention. The transmission character control register (TCR) stores the received FIFO threshold levels for starting or stopping transmission during flow control. The FIFO RDY register provides TXRDY\/RXRDY status for both ports in a single read. Full modem control signals (CTS, RTS, DSR, DTR, RI, CD) are available for each channel. Additional features include IrDA SIR encoder\/decoder, RS-485 mode, programmable sleep mode, and internal loopback for diagnostics.","working_principle":"The TL16C752DPFBR integrates two independent UART channels with shared bus interface. (1) Parallel-to-Serial Conversion: The CPU writes parallel data bytes to the UART transmit holding register (THR). The UART adds the programmed start bit, parity bit, and stop bits, then shifts the data out serially on the TX pin at the programmed baud rate. (2) Serial-to-Parallel Conversion: The UART detects the start bit, samples the incoming data bits at the center of each bit period, checks parity and stop bits, and places the received byte in the receive buffer register (RBR) for CPU reading. (3) Baud Rate Generation: Each channel has a programmable baud rate generator that divides the input clock (XTAL1) by a 16-bit divisor to produce the desired baud rate x16 clock. A prescaler provides an additional divide-by-4 option. (4) FIFO Operation: The 64-byte TX FIFO buffers data written by the CPU, while the 64-byte RX FIFO buffers received data. Programmable trigger levels generate interrupts or DMA requests when the FIFO reaches the threshold. (5) Flow Control: Auto-RTS deasserts RTS when the RX FIFO reaches the halt threshold. Auto-CTS waits for CTS assertion before transmitting. Software flow control sends XOFF\/XON characters automatically.","pin_description":"
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