{"id":6849,"date":"2026-06-21T13:09:27","date_gmt":"2026-06-21T13:09:27","guid":{"rendered":"https:\/\/materialparts.com\/74hc138pw\/"},"modified":"2026-06-21T13:09:27","modified_gmt":"2026-06-21T13:09:27","slug":"74hc138pw","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/74hc138pw\/","title":{"rendered":"74HC138PW"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The 74HC138PW is a 3-to-8 line decoder\/demultiplexer with inverting outputs, designed for memory decoding and data routing applications in a TSSOP-16 package.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n\n
\u0627\u0644\u0646\u0648\u0639<\/td>\n3-to-8 Line Decoder \/ Demultiplexer<\/td>\n<\/tr>\n
\u0627\u0644\u0648\u0638\u064a\u0641\u0629<\/td>\n3-bit binary to 1-of-8 decoder, active LOW outputs<\/td>\n<\/tr>\n
\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n12 ns (typical @ 6V)<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n2.0 V to 6.0 V (74HC)<\/td>\n<\/tr>\n
Output Drive<\/td>\n+\/-5.2 mA @ 6V<\/td>\n<\/tr>\n
Enable Inputs<\/td>\n3 (2 active LOW, 1 active HIGH)<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nTSSOP-16 (4.4mm width)<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n-40C to +125C<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • 3-to-8 decoder with active LOW outputs<\/li>\n
  • 3 enable inputs for expansion capability<\/li>\n
  • 12 ns typical propagation delay<\/li>\n
  • 2V to 6V supply range<\/li>\n
  • Memory address decoding<\/li>\n
  • Demultiplexing capability<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Memory address decoding<\/li>\n
    • Data demultiplexing<\/li>\n
    • Chip select generation<\/li>\n
    • Clock distribution<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The 74HC138PW is a 3-to-8 line decoder\/demultiplexer with inverting outputs, designed for memory decoding and data routing applications in a TSSOP-16 package. Key Specifications Type 3-to-8 Line Decoder \/ Demultiplexer Function 3-bit binary to 1-of-8 decoder, active LOW outputs Propagation Delay 12 ns (typical @ 6V) Supply Voltage 2.0 V to 6.0 V […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[140],"class_list":["post-6849","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-nexperia"],"acf":{"brief_explanation":"3-to-8 Decoder\/Demux, Active LOW Out, TSSOP-16, 74HC","date_code":"","package_case":"TSSOP-16 (5.0 x 4.4 x 1.0 mm)","in_stock":45678,"datasheet":"https:\/\/assets.nexperia.com\/documents\/data-sheet\/74HC_HCT138.pdf","price":"$0.20 @ 1ku","product_introduction":"The 74HC138PW is a high-speed CMOS 3-to-8 line decoder\/demultiplexer with active LOW outputs. The device accepts a 3-bit binary address (A0, A1, A2) and activates one of eight mutually exclusive outputs (Y0 to Y7). Three enable inputs (two active LOW E1, E2 and one active HIGH E3) facilitate expansion to larger decoder configurations: four 74HC138 devices plus one inverter can implement a 1-of-32 decoder. The device is widely used for memory address decoding, chip select generation, and data demultiplexing in digital systems. The TSSOP-16 package provides a compact footprint for modern PCB designs. Note: This model number without manufacturer-specific ordering suffix is a generic 74HC138PW listing; the Nexperia version with full ordering code 74HC138PW,118 was already published in Group 6 (Article ID 6788).","working_principle":"The 74HC138PW uses internal NAND gates to decode the 3-bit address. Each output Y(n) is activated (driven LOW) when the address inputs match the binary value n (0-7) AND all enable conditions are met (E1=LOW, E2=LOW, E3=HIGH). If any enable condition is not satisfied, all outputs remain HIGH (inactive). The propagation delay of approximately 12 ns at 6V is determined by the two levels of logic gates between the address inputs and outputs. The enable inputs serve dual purposes: they prevent glitching during address transitions (by disabling the outputs during the transition), and they allow cascading for address expansion. In demultiplexer mode, the data input is applied to one of the enable inputs (typically E3), and the address selects which output receives the data. The active LOW outputs are directly compatible with active LOW chip select inputs on memory and peripheral ICs.","pin_description":"
      Pin<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>
      1<\/td>A0<\/td>Input<\/td>Address input bit 0 (LSB)<\/td><\/tr>
      2<\/td>A1<\/td>Input<\/td>Address input bit 1<\/td><\/tr>
      3<\/td>A2<\/td>Input<\/td>Address input bit 2 (MSB)<\/td><\/tr>
      4<\/td>E1<\/td>Input<\/td>Enable input (active LOW)<\/td><\/tr>
      5<\/td>E2<\/td>Input<\/td>Enable input (active LOW)<\/td><\/tr>
      6<\/td>E3<\/td>Input<\/td>Enable input (active HIGH)<\/td><\/tr>
      7-9<\/td>Y7-Y5<\/td>Output<\/td>Decoded outputs (active LOW)<\/td><\/tr>
      10<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>
      11-13<\/td>Y4-Y2<\/td>Output<\/td>Decoded outputs (active LOW)<\/td><\/tr>
      14<\/td>Y1<\/td>Output<\/td>Decoded output (active LOW)<\/td><\/tr>
      15<\/td>Y0<\/td>Output<\/td>Decoded output (active LOW)<\/td><\/tr>
      16<\/td>VCC<\/td>Power<\/td>Supply (2-6V)<\/td><\/tr><\/table>","application_scenarios":"
      • 8-device chip select decoder from 3-bit MCU address bus<\/li>
      • Memory bank selection using 2 enable inputs for 4-bank expansion<\/li>
      • Clock distribution demultiplexer routing clock to 1 of 8 destinations<\/li>
      • 1-of-32 decoder using 4x 74HC138 + 1 inverter for 5-bit address<\/li><\/ul>","alternative_models":"
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>
        Nexperia<\/td>74HC138PW,118<\/td>TSSOP-16<\/td>Full Nexperia ordering code (same device)<\/td><\/tr>
        TI<\/td>SN74HC138PWR<\/td>TSSOP-16<\/td>Pin-compatible TI equivalent<\/td><\/tr>
        onsemi<\/td>MC74HC138ADR2G<\/td>SOIC-16<\/td>Same function, SOIC package<\/td><\/tr>
        Nexperia<\/td>74HC238PW,118<\/td>TSSOP-16<\/td>Same but active HIGH outputs<\/td><\/tr>
        Nexperia<\/td>74HC154D,653<\/td>SOIC-24<\/td>4-to-16 decoder, larger function<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/6849","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=6849"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/6849\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=6849"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=6849"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=6849"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=6849"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}