The ADS8320E\/2K5 from TI is a 16-bit 100kSPS SAR ADC with SPI interface, 2.7-5.25V supply, and 1.8mW power consumption in VSSOP-8 for precision data acquisition.<\/p>\n
| \u0627\u0644\u062d\u0632\u0645\u0629<\/td>\n | VSSOP-8 (3x3mm)<\/td>\n<\/tr>\n<\/table>\n\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\nProduct Overview The ADS8320E\/2K5 from TI is a 16-bit 100kSPS SAR ADC with SPI interface, 2.7-5.25V supply, and 1.8mW power consumption in VSSOP-8 for precision data acquisition. Key Specifications Package VSSOP-8 (3x3mm) Features See datasheet for complete specifications Industry-standard package Applications Industrial control Consumer electronics Communication equipment Power management<\/p>","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[],"chip_brand":[138],"class_list":["post-5873","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"16-bit 100kSPS ADC, SPI, 2.7-5.25V, VSSOP-8","date_code":"","package_case":"VSSOP-8 (3x3mm)","in_stock":12033,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/ads8320.pdf","price":"$4.00 @ 1ku","product_introduction":"The ADS8320E\/2K5 from TI is a 16-bit 100kSPS SAR ADC with SPI interface, 2.7-5.25V supply, and 1.8mW power consumption in VSSOP-8 for precision data acquisition.","working_principle":"The ADS8320E\/2K5 is a 16-bit 100kSPS SAR (Successive Approximation Register) ADC from TI in VSSOP-8, operating from 2.7V to 5.25V with SPI-compatible serial interface. The SAR conversion algorithm works by: 1) Sample the analog input on an internal hold capacitor (conversion starts on CS falling edge); 2) The 16-bit SAR register starts at MSB = 1, all others = 0; 3) The internal DAC converts this digital code to an analog voltage; 4) The comparator determines if the DAC output is higher or lower than the held input; 5) If DAC > input, MSB = 0; if DAC < input, MSB stays 1; 6) Repeat for each bit from MSB to LSB (16 comparisons total). The entire conversion takes 16 DCLK cycles plus 2 overhead cycles = 18 DCLK periods. At 2.4MHz DCLK, this gives 100kSPS throughput. The external VREF pin sets the full-scale range: VIN ranges from COM to VREF. Using a 2.5V reference gives 0-2.5V input range with 38uV LSB step size (2.5V \/ 65536). The \/2K5 suffix denotes the 100kSPS speed grade and tape-and-reel packaging. The SHDN pin (active LOW) reduces power from 4.5mW to 0.3uW. The SPI interface is compatible with most MCUs: CS frames the conversion, DCLK shifts out data on DOUT MSB-first, with the first clock outputting the MSB result of the previous conversion.","pin_description":"
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