The TPS51200DRCR from Texas Instruments is a DDR termination regulator with 2A sink\/source capability, VTT and VREF outputs, and 3.3V\/5V supply in a 10-pin VSON package.<\/p>\n
| \u0627\u0644\u0648\u0638\u064a\u0641\u0629<\/td>\n | DDR Termination Regulator (VTT + VREF)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| Input Supply (VDD)<\/td>\n | 3.3V or 5V<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| VTT Output Current<\/td>\n | +\/-2A (sink and source)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| VTT Output Voltage<\/td>\n | Half of VDDQ (0.9V for DDR3 at 1.5V VDDQ)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| VREF Output<\/td>\n | VDDQ\/2 (1mA drive capability)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| Accuracy<\/td>\n | +\/-10mV VTT, +\/-5mV VREF<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| \u062a\u064a\u0627\u0631 \u0625\u064a\u0642\u0627\u0641 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n | 0.5uA (typical)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| \u0627\u0644\u062d\u0632\u0645\u0629<\/td>\n | VSON-10 (3mm x 3mm)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||||||
| \u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n | -40 to +85 C<\/td>\n<\/tr>\n<\/table>\n\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\nProduct Overview The TPS51200DRCR from Texas Instruments is a DDR termination regulator with 2A sink\/source capability, VTT and VREF outputs, and 3.3V\/5V supply in a 10-pin VSON package. Key Specifications Function DDR Termination Regulator (VTT + VREF) Input Supply (VDD) 3.3V or 5V VTT Output Current +\/-2A (sink and source) VTT Output Voltage Half of […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,29],"tags":[],"chip_brand":[138],"class_list":["post-3818","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-power-management-ics-pmic","chip_brand-ti"],"acf":{"brief_explanation":"DDR termination regulator, +\/-2A VTT, VREF output, VSON-10","date_code":"","package_case":"VSON-10 (3 x 3 x 0.8 mm, DRC package, 0.5mm pitch)","in_stock":4540,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/tps51200.pdf","price":"$0.90 @ 1ku","product_introduction":"The TPS51200DRCR from Texas Instruments is a dedicated DDR memory termination regulator that generates both the VTT termination voltage and the VREF reference voltage required by DDR, DDR2, and DDR3 memory systems. The VTT output is a low-impedance voltage source set to half the VDDQ supply voltage (e.g., 0.9V for DDR3 with 1.8V VDDQ, or 0.75V for DDR3L with 1.5V VDDQ), capable of sourcing and sinking up to 2A. This sink\/source capability is essential for DDR termination, where data line transitions cause current to flow both into and out of the termination voltage rail. The +\/-10mV VTT accuracy ensures reliable signal integrity across the memory bus. The VREF output provides a separate VDDQ\/2 reference with +\/-5mV accuracy for the memory controller's reference input. The device operates from a 3.3V or 5V input supply and tracks the VDDQ voltage through the VSNS input pin, ensuring VTT and VREF remain at exactly VDDQ\/2 even as VDDQ varies during power-up and power-down sequences. The PGOOD output indicates when VTT is within specification. The S5 (sleep) pin reduces power consumption during system sleep modes.","working_principle":"The TPS51200DRCR operates as a DDR termination voltage regulator. Key subsystems include: (1) VTT Regulator - a linear regulator with integrated N-channel and P-channel MOSFETs for sourcing and sinking current; the output voltage is set to VSNS\/2 (half the sensed VDDQ voltage) by an internal resistor divider; the regulator uses a high-gain error amplifier to maintain VTT at the target value with +\/-10mV accuracy; the 2A sink\/source capability is achieved by paralleling multiple MOSFET segments; (2) VREF Buffer - a precision voltage buffer that generates VDDQ\/2 with +\/-5mV accuracy; the VREF output is derived from the same VSNS\/2 divider as VTT but through a separate buffer with lower drive capability (1mA); the separate buffer prevents VTT load transients from affecting the VREF stability; (3) VSNS Input - the VSNS pin connects to the VDDQ rail and is used by the internal divider to generate VDDQ\/2; the high-impedance VSNS input draws minimal current from VDDQ; (4) PGOOD Output - a power-good open-drain output that is asserted high (after a 1ms delay) when VTT is within +\/-5% of the target value; PGOOD de-asserts immediately when VTT goes out of specification; (5) S5 (Sleep) Input - when S5 is asserted high, the VTT and VREF outputs are disabled and the device enters low-power mode (0.5uA shutdown current); this is used during system sleep states where memory is in self-refresh mode and termination is not needed.","pin_description":"
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