{"id":3766,"date":"2026-06-08T03:23:10","date_gmt":"2026-06-08T03:23:10","guid":{"rendered":"https:\/\/materialparts.com\/74hc595d118\/"},"modified":"2026-06-08T03:23:10","modified_gmt":"2026-06-08T03:23:10","slug":"74hc595d118","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/74hc595d118\/","title":{"rendered":"74HC595D,118"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The 74HC595D,118 from Nexperia is an 8-bit serial-in\/serial-or-parallel-out shift register with output latches and 3-state outputs, supporting 100MHz shift frequency in a 16-pin SOIC package.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\u0627\u0644\u0648\u0638\u064a\u0641\u0629<\/td>\n8-Bit Shift Register with Output Latches<\/td>\n<\/tr>\n
Bits<\/td>\n8<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n2V to 6V<\/td>\n<\/tr>\n
Shift Frequency<\/td>\n100 MHz (typ, VCC=5V)<\/td>\n<\/tr>\n
\u0646\u0648\u0639 \u0627\u0644\u0625\u062e\u0631\u0627\u062c<\/td>\n3-\u0627\u0644\u062f\u0648\u0644\u0629<\/td>\n<\/tr>\n
Output Drive<\/td>\n+\/-7.8 mA @ 5V<\/td>\n<\/tr>\n
\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n14-35 ns (typ, VCC=4.5V)<\/td>\n<\/tr>\n
Clock Inputs<\/td>\nSHCP (shift), STCP (storage)<\/td>\n<\/tr>\n
Serial Output<\/td>\nQ7S (for cascading)<\/td>\n<\/tr>\n
Master Reset<\/td>\nMR (active LOW, asynchronous)<\/td>\n<\/tr>\n
Output Enable<\/td>\nOE (active LOW)<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nSOIC-16 (3.9mm width)<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n-40 to +125 C<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • 8-bit serial input, 8-bit parallel output with latch<\/li>\n
  • Separate shift and storage register clocks<\/li>\n
  • Serial output Q7S for daisy-chaining<\/li>\n
  • 3-state outputs for bus sharing<\/li>\n
  • Asynchronous master reset (MR)<\/li>\n
  • 100MHz typical shift frequency<\/li>\n
  • Input clamp diodes for voltage translation<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • LED matrix and display driving (multiplexing)<\/li>\n
    • Expanding MCU GPIO pins via SPI<\/li>\n
    • Serial-to-parallel data conversion<\/li>\n
    • Cascaded display register chains<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The 74HC595D,118 from Nexperia is an 8-bit serial-in\/serial-or-parallel-out shift register with output latches and 3-state outputs, supporting 100MHz shift frequency in a 16-pin SOIC package. Key Specifications Function 8-Bit Shift Register with Output Latches Bits 8 Supply Voltage 2V to 6V Shift Frequency 100 MHz (typ, VCC=5V) Output Type 3-State Output Drive +\/-7.8 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[],"chip_brand":[168],"class_list":["post-3766","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","chip_brand-nxp"],"acf":{"brief_explanation":"8-bit shift register with latch, 3-state out, 100MHz, cascade, SOIC-16","date_code":"","package_case":"SOIC-16 (10 x 3.9 x 1.58 mm, SOT109-1)","in_stock":11276,"datasheet":"https:\/\/assets.nexperia.com\/documents\/data-sheet\/74HC_HCT595.pdf","price":"$0.30 @ 1ku","product_introduction":"The 74HC595D,118 from Nexperia is an 8-bit serial-in\/serial-or-parallel-out shift register with separate shift and storage registers, 3-state outputs, and daisy-chain capability. The device accepts serial data on the DS (data serial) input, clocked in on the rising edge of the SHCP (shift clock) input. After 8 bits have been shifted in, the STCP (storage clock) rising edge transfers the shift register contents to the storage register, which drives the 8 parallel outputs (Q0-Q7). The 3-state output enable (OE, active LOW) allows multiple 74HC595 devices to share the same output bus or to disable outputs during system initialization. A serial output (Q7S) provides the data shifted out of the 8th stage, enabling daisy-chaining of multiple devices for 16-bit, 24-bit, or wider output registers using only 3 MCU pins (DS, SHCP, STCP). The asynchronous master reset (MR, active LOW) clears the shift register independently of the clocks. The 74HC595 is one of the most popular logic ICs for expanding GPIO pins on microcontrollers, driving LED matrices, 7-segment displays, and relay boards. The ,118 suffix indicates Nexperia's tape-and-reel packaging. The device operates from 2V to 6V supply with typical shift frequencies of 100MHz at 5V, far exceeding the requirements of typical SPI interfaces.","working_principle":"The 74HC595D,118 operates as a serial-to-parallel converter with separate shift and storage registers. Key subsystems include: (1) Shift Register - 8 flip-flops connected in series; data on the DS input is captured on the rising edge of SHCP and shifted through each stage; after 8 SHCP pulses, all 8 bits of serial data occupy the shift register; the Q7S output reflects the data shifted out of stage 8, enabling cascading to the next device; (2) Storage Register - 8 D-type latches in parallel; on the rising edge of STCP, the current contents of the shift register are transferred to the storage register; this dual-register architecture allows new data to be shifted in while the previous data remains displayed on the outputs; (3) 3-State Outputs - the storage register outputs are buffered through 3-state output drivers controlled by the OE pin; when OE is LOW, the outputs reflect the storage register data; when OE is HIGH, the outputs are high-impedance; this allows bus sharing and controlled output activation; (4) Master Reset - the MR input asynchronously clears the shift register (all stages to LOW) when driven LOW; the storage register is not affected by MR; to clear both registers, assert MR then pulse STCP; (5) Cascading - the Q7S output connects to the DS input of the next 74HC595 in the chain; all devices share the same SHCP and STCP lines; after shifting 16 bits (for 2 devices), 24 bits (for 3), etc., a single STCP pulse updates all outputs simultaneously.","pin_description":"
      Pin<\/th>Name<\/th>Function<\/th><\/tr>
      1<\/td>Q1<\/td>Parallel output bit 1<\/td><\/tr>
      2<\/td>Q2<\/td>Parallel output bit 2<\/td><\/tr>
      3<\/td>Q3<\/td>Parallel output bit 3<\/td><\/tr>
      4<\/td>Q4<\/td>Parallel output bit 4<\/td><\/tr>
      5<\/td>Q5<\/td>Parallel output bit 5<\/td><\/tr>
      6<\/td>Q6<\/td>Parallel output bit 6<\/td><\/tr>
      7<\/td>Q7<\/td>Parallel output bit 7<\/td><\/tr>
      8<\/td>GND<\/td>Ground<\/td><\/tr>
      9<\/td>Q7S<\/td>Serial output (for cascading to next DS)<\/td><\/tr>
      10<\/td>MR<\/td>Master reset (active LOW, clears shift register)<\/td><\/tr>
      11<\/td>SHCP<\/td>Shift register clock (rising edge shifts data)<\/td><\/tr>
      12<\/td>STCP<\/td>Storage register clock (rising edge latches data)<\/td><\/tr>
      13<\/td>OE<\/td>Output enable (active LOW; HIGH = high-Z outputs)<\/td><\/tr>
      14<\/td>DS<\/td>Serial data input<\/td><\/tr>
      15<\/td>Q0<\/td>Parallel output bit 0<\/td><\/tr>
      16<\/td>VCC<\/td>Supply voltage (2V to 6V)<\/td><\/tr><\/table>","application_scenarios":"
      • LED matrix driver: 2x 74HC595 cascade drives 8x8 LED matrix (8 anodes + 8 cathodes) from 3 MCU pins<\/li>
      • 7-segment multiplex: 4-digit display with 2 cascaded 74HC595 (digit select + segment data)<\/li>
      • Relay board: 8-channel relay module controlled via SPI from single GPIO<\/li>
      • GPIO expansion: add 8+ digital outputs to Arduino\/RPi with 3-wire SPI interface<\/li><\/ul>","alternative_models":"
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>
        TI<\/td>SN74HC595DWR<\/td>SOIC-16<\/td>TI version, wide SOIC<\/td><\/tr>
        Nexperia<\/td>74HC595PW,118<\/td>TSSOP-16<\/td>Smaller TSSOP package<\/td><\/tr>
        Microchip<\/td>74HC595D<\/td>SOIC-16<\/td>Microchip version<\/td><\/tr>
        Nexperia<\/td>74HCT595D,118<\/td>SOIC-16<\/td>TTL-compatible input thresholds<\/td><\/tr>
        TI<\/td>TPIC6B595DWR<\/td>SOIC-20<\/td>Power shift register, 50mA\/50V open-drain<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/3766","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=3766"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/3766\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=3766"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=3766"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=3766"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=3766"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}