\u0625\u0646 TLA2024IRUGT \u0645\u0646 Texas Instruments \u0639\u0628\u0627\u0631\u0629 \u0639\u0646 ADC ADC \u0631\u0628\u0627\u0639\u064a \u0627\u0644\u0642\u0646\u0648\u0627\u062a \u062f\u0644\u062a\u0627 \u0633\u064a\u062c\u0645\u0627 12 \u0628\u062a \u0645\u0639 \u0648\u0627\u062c\u0647\u0629 I2C \u0641\u064a \u062d\u0632\u0645\u0629 X2QFN \u0630\u0627\u062a 10 \u0633\u0646\u0648\u0646 (2.0 \u00d7 1.5 \u0645\u0645). \u0648\u064a\u062a\u0645\u064a\u0632 \u0628\u0645\u0636\u0627\u0639\u0641\u0627\u062a \u0625\u062f\u062e\u0627\u0644 \u0645\u0631\u0646\u0629 (4 \u0623\u062d\u0627\u062f\u064a \u0627\u0644\u0637\u0631\u0641 \u0623\u0648 2 \u062a\u0641\u0627\u0636\u0644\u064a)\u060c \u0648\u0645\u0636\u062e\u0645 \u0643\u0633\u0628 \u0642\u0627\u0628\u0644 \u0644\u0644\u0628\u0631\u0645\u062c\u0629 (1x\/2x\/4x\/8x \u0625\u0644\u0649 x16)\u060c \u0648\u0645\u0631\u062c\u0639 \u062c\u0647\u062f \u062f\u0627\u062e\u0644\u064a\u060c \u0648\u0645\u0630\u0628\u0630\u0628 \u062f\u0627\u062e\u0644\u064a\u060c \u0648\u0645\u0639\u062f\u0644 \u0628\u064a\u0627\u0646\u0627\u062a 128 SPS \u0625\u0644\u0649 3.3 \u0643\u064a\u0644\u0648 \u062b\u0627\u0646\u064a\u0629 \u0641\u064a \u0627\u0644\u062b\u0627\u0646\u064a\u0629\u060c \u0648\u062a\u064a\u0627\u0631 \u0625\u0645\u062f\u0627\u062f 150 uA\u060c \u0648\u0646\u0637\u0627\u0642 \u0625\u0645\u062f\u0627\u062f \u0645\u0646 2 \u0641\u0648\u0644\u062a \u0625\u0644\u0649 5.5 \u0641\u0648\u0644\u062a\u060c \u06483 \u0639\u0646\u0627\u0648\u064a\u0646 I2C \u0642\u0627\u0628\u0644\u0629 \u0644\u0644\u062a\u062d\u062f\u064a\u062f \u0628\u062f\u0628\u0648\u0633. \u062a\u062d\u0648\u064a\u0644 \u0623\u062d\u0627\u062f\u064a \u0627\u0644\u0644\u0642\u0637\u0629 \u0623\u0648 \u062a\u062d\u0648\u064a\u0644 \u0645\u0633\u062a\u0645\u0631. \u0627\u0633\u062a\u0647\u0644\u0627\u0643 \u0637\u0627\u0642\u0629 \u0646\u0645\u0648\u0630\u062c\u064a 0.9 \u0645\u064a\u062c\u0627\u0648\u0627\u062a. \u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644 -40 \u062f\u0631\u062c\u0629 \u0645\u0626\u0648\u064a\u0629 \u0625\u0644\u0649 +85 \u062f\u0631\u062c\u0629 \u0645\u0626\u0648\u064a\u0629. \u062a\u063a\u0644\u064a\u0641 \u0639\u0644\u0649 \u0634\u0631\u064a\u0637 \u0648\u0628\u0643\u0631\u0629.<\/p>","protected":false},"excerpt":{"rendered":"
The TLA2024IRUGT from Texas Instruments is a 12-bit 4-channel delta-sigma ADC with I2C interface in a 10-pin X2QFN package (2.0 x 1.5 mm). It features a flexible input multiplexer (4 single-ended or 2 differential), programmable gain amplifier (1x\/2x\/4x\/8x to x16), internal voltage reference, internal oscillator, 128 SPS to 3.3 kSPS data rate, 150 uA supply […]<\/p>\n","protected":false},"author":2,"featured_media":2248,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-2084","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"12-bit 4ch delta-sigma ADC, PGA x1-16, I2C, int ref, X2QFN 2x1.5mm, T\/R","date_code":"","package_case":"10-X2QFN (2.05 x 1.55 x 0.35 mm, 0.5mm pitch, leadless)","in_stock":1380,"datasheet":"https:\/\/www.ti.com\/product\/TLA2024","price":"$1.06 (250+ pcs)","product_introduction":"The TLA2024IRUGT from Texas Instruments is an ultra-small, cost-optimized 12-bit delta-sigma ADC with 4-channel input multiplexer and programmable gain amplifier in a 10-pin X2QFN package measuring just 2.0 x 1.5 mm. It is the highest-channel-density variant of the TLA202x family, offering 4 single-ended or 2 differential input channels at only 0.75 mm2 per channel.\n\nThe TLA2024 features a flexible input multiplexer that can be configured as four single-ended inputs (AIN0-GND, AIN1-GND, AIN2-GND, AIN3-GND) or two differential input pairs (AIN0-AIN1, AIN2-AIN3). The multiplexer is software-configurable via the I2C interface, allowing sequential scanning of multiple input channels.\n\nThe integrated programmable gain amplifier (PGA) provides gain settings of x1, x2, x4, x8, and x16 (note: some sources list up to x16 while others list x8 maximum). At maximum PGA gain, the input range is reduced to +\/-256 mV (at x8) or +\/-128 mV (at x16), enabling direct measurement of small signals from current sense resistors, thermocouples, and bridge sensors without external amplification. The PGA has input ranges from +\/-6.144V (x1) down to +\/-256 mV (x8).\n\nThe device integrates a voltage reference, oscillator, and I2C interface. The internal 2.048V reference provides the ADC full-scale reference. The I2C interface supports standard mode and fast mode, with three pin-selectable addresses.\n\nThe TLA2024 provides 12-bit resolution with programmable data rates from 128 SPS to 3.3 kSPS. The delta-sigma architecture provides inherent anti-aliasing and good noise performance. INL is 1 LSB typical, and full-scale error is 0.05% FSR typical. No missing codes are guaranteed to 12 bits.\n\nThe 0.9 mW typical power consumption and single-shot conversion mode make the TLA2024 suitable for power-constrained applications. In single-shot mode, the device automatically powers down after each conversion, reducing average current to microamps at low sampling rates.\n\nThe X2QFN package has a land pattern of only 3 mm2, making it the industry's smallest 4-channel 12-bit ADC. This enables placement directly at sensor nodes in space-constrained systems.\n\nThe TLA2024 shares the same datasheet (SBAS975) with the TLA2021 and TLA2022. The key differences are: TLA2021 = 1-channel, no PGA; TLA2022 = 1-channel with PGA; TLA2024 = 4-channel with PGA and MUX.","working_principle":"**Delta-Sigma ADC with PGA and MUX:** The input signal first passes through the analog multiplexer, which selects one of four single-ended or two differential input configurations. The selected signal is then amplified by the PGA, digitized by the delta-sigma modulator, and filtered by the SINC digital decimation filter to produce a 12-bit output word.\n\n**Input Multiplexer:** The 4:1 (single-ended) or 2:1 (differential) multiplexer is controlled by the MUX[2:0] bits in the configuration register. Channel switching requires a settling time before the conversion result is valid, typically one conversion cycle.\n\n**PGA Operation:** The PGA amplifies the input signal before the modulator. At x1 gain, the full-scale input range is +\/-6.144V (well beyond VDD, but limited by absolute maximum ratings to VDD+0.3V). At x2: +\/-4.096V. At x4: +\/-2.048V. At x8: +\/-1.024V (some sources: +\/-256mV). Higher gain reduces the input range but improves the effective resolution for small signals. The PGA input common-mode range must be within GND-0.1V to VDD+0.1V.\n\n**Conversion and Data Format:** The 12-bit conversion result is output in 16-bit two's complement format, left-justified. At PGA = x1, 1 LSB = 187.5 uV (6.144V \/ 32768). At PGA = x8, 1 LSB = 23.4 uV (1.024V \/ 32768, if 12-bit effective).\n\n**I2C Protocol:** Write to the 16-bit configuration register to set MUX, PGA, mode, and data rate. Read 2 bytes (16 bits) for conversion result. The OS bit starts a single-shot conversion when written as 1. The ALERT\/RDY pin can signal conversion completion or out-of-range conditions.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| A1<\/td> | AIN0<\/td> | I<\/td> | Analog input 0; positive input for differential pair 0; single-ended input 0; 0 to VDD range; MUX selectable<\/td><\/tr> | ||||||||||||||||||||||||
| A2<\/td> | AIN1<\/td> | I<\/td> | Analog input 1; negative input for differential pair 0; single-ended input 1; 0 to VDD range; MUX selectable<\/td><\/tr> | ||||||||||||||||||||||||
| B1<\/td> | GND<\/td> | G<\/td> | Ground; connect to PCB ground plane<\/td><\/tr> | ||||||||||||||||||||||||
| B2<\/td> | ADDR<\/td> | I<\/td> | I2C address select; GND = 0x48; VDD = 0x49; SDA = 0x4A; must be tied to defined state<\/td><\/tr> | ||||||||||||||||||||||||
| C1<\/td> | SDA<\/td> | I\/O<\/td> | I2C data; open-drain; requires external pull-up (4.7kOhm typical); fast-mode compatible<\/td><\/tr> | ||||||||||||||||||||||||
| C2<\/td> | SCL<\/td> | I<\/td> | I2C clock; requires external pull-up (4.7kOhm typical); up to 400kHz<\/td><\/tr> | ||||||||||||||||||||||||
| D1<\/td> | ALERT\/RDY<\/td> | O<\/td> | Alert\/Ready output; active-low open-drain; conversion complete or comparator threshold exceeded; connect pull-up if used<\/td><\/tr> | ||||||||||||||||||||||||
| D2<\/td> | VDD<\/td> | P<\/td> | Supply voltage; 2V to 5.5V; decouple with 0.1uF ceramic to GND<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|