\u0625\u0646 SN74LVC2G74DCUR \u0645\u0646 Texas Instruments \u0639\u0628\u0627\u0631\u0629 \u0639\u0646 \u062f\u0648\u0627\u0631\u0629 \u0642\u0644\u0627\u0628\u0629 \u0645\u0646 \u0627\u0644\u0646\u0648\u0639 D \u0630\u0627\u062a \u062d\u0627\u0641\u0629 \u0645\u0648\u062c\u0628\u0629 \u0645\u0646 \u0627\u0644\u0646\u0648\u0639 D \u0645\u0639 \u0645\u0633\u062d \u063a\u064a\u0631 \u0645\u062a\u0632\u0627\u0645\u0646 \u0648\u062a\u0639\u064a\u064a\u0646 \u0645\u0633\u0628\u0642 \u0641\u064a \u062d\u0632\u0645\u0629 VSSOP (DCU) \u0630\u0627\u062a 8 \u0633\u0646\u0648\u0646 \u0628\u0642\u064a\u0627\u0633 2.3 \u00d7 2.0 \u0645\u0645. \u064a\u0639\u0645\u0644 \u0627\u0644\u062c\u0647\u0627\u0632 \u0645\u0646 1.65 \u0641\u0648\u0644\u062a \u0625\u0644\u0649 5.5 \u0641\u0648\u0644\u062a \u0645\u0639 \u062a\u0623\u062e\u064a\u0631 \u0627\u0646\u062a\u0634\u0627\u0631 \u0623\u0642\u0635\u0649 \u064a\u0628\u0644\u063a 5.9 \u0646\u0627\u0646\u0648\u0645\u062a\u0631 \u0639\u0646\u062f 3.3 \u0641\u0648\u0644\u062a \u06484.4 \u0646\u0627\u0646\u0648\u0645\u062a\u0631 \u0639\u0646\u062f 5 \u0641\u0648\u0644\u062a. \u064a\u062a\u0645\u064a\u0632 \u0627\u0644\u062c\u0647\u0627\u0632 \u0628\u0645\u062e\u0631\u062c\u0627\u062a \u062a\u0643\u0645\u064a\u0644\u064a\u0629 Q \u0648 Q\u060c \u0648\u0645\u062d\u0631\u0643 \u0625\u062e\u0631\u0627\u062c \u00b1 24 \u0645\u0644\u0644\u064a \u0623\u0645\u0628\u064a\u0631 \u0639\u0646\u062f 3.3 \u0641\u0648\u0644\u062a\u060c \u0648\u062a\u064a\u0627\u0631 \u0647\u0627\u062f\u0626 \u0628\u062d\u062f \u0623\u0642\u0635\u0649 10 \u0645\u064a\u062c\u0627 \u0623\u0645\u0628\u064a\u0631\u060c \u0648\u062a\u0631\u062f\u062f \u0633\u0627\u0639\u0629 \u064a\u0635\u0644 \u0625\u0644\u0649 200 \u0645\u064a\u062c\u0627\u0647\u0631\u062a\u0632. \u062a\u062f\u0639\u0645 \u062f\u0627\u0631\u0629 \u0625\u064a\u0642\u0627\u0641 \u0627\u0644\u062a\u0634\u063a\u064a\u0644 \u062a\u0637\u0628\u064a\u0642\u0627\u062a \u062e\u0641\u0636 \u0627\u0644\u0637\u0627\u0642\u0629 \u0627\u0644\u062c\u0632\u0626\u064a \u0648\u0627\u0644\u0625\u062f\u062e\u0627\u0644 \u0627\u0644\u0645\u0628\u0627\u0634\u0631. \u064a\u062a\u0631\u0627\u0648\u062d \u0646\u0637\u0627\u0642 \u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644 \u0645\u0646 -40 \u062f\u0631\u062c\u0629 \u0645\u0626\u0648\u064a\u0629 \u0625\u0644\u0649 +125 \u062f\u0631\u062c\u0629 \u0645\u0626\u0648\u064a\u0629 \u0644\u0644\u0644\u0627\u062d\u0642\u0629 DCUR.<\/p>","protected":false},"excerpt":{"rendered":"
The SN74LVC2G74DCUR from Texas Instruments is a single positive-edge-triggered D-type flip-flop with asynchronous clear and preset in an 8-pin VSSOP (DCU) package measuring 2.3\u00d72.0 mm. It operates from 1.65 V to 5.5 V with maximum propagation delay of 5.9 ns at 3.3 V and 4.4 ns at 5 V. The device features complementary Q and […]<\/p>\n","protected":false},"author":2,"featured_media":2875,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,15],"tags":[],"chip_brand":[138],"class_list":["post-2042","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-logic-chips","chip_brand-ti"],"acf":{"brief_explanation":"Single D-FF, preset+clear, 1.65-5.5V, 200MHz, 4.4ns@5V, \u00b124mA, VSSOP-8, -40~125\u00b0C","date_code":"","package_case":"VSSOP-8 (DCU) (2.3 x 2.0 x 0.9 mm, 0.5mm pitch)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74lvc2g74.pdf","price":"$0.38 (1K+ pcs)","product_introduction":"The SN74LVC2G74 is a single positive-edge-triggered D-type flip-flop from TI's 74LVC logic family, offering asynchronous preset (PRE) and clear (CLR) inputs with complementary Q and Q-bar outputs. Despite the '2G' prefix (indicating a 2-gate device in the LVC family), this part contains a single flip-flop element with both preset and clear \u2014 the '2G' refers to the approximate gate count, not the number of flip-flops.\n\nThe device operates across a wide voltage range of 1.65 V to 5.5 V, making it suitable for mixed-voltage systems. At 5 V, the maximum propagation delay is 4.4 ns with a 50-pF load, and the maximum clock frequency reaches 200 MHz. The setup time is only 1.1 ns and hold time is 500 ps at 5 V, enabling high-speed synchronous designs.\n\nThe asynchronous preset input (PRE, active low) sets Q high regardless of clock and data inputs. The asynchronous clear input (CLR, active low) sets Q low regardless of other inputs. When both PRE and CLR are inactive (high), data at the D input is transferred to Q on the rising edge of CLK. This independent preset\/clear capability is useful for power-on initialization, manual reset, and handshake circuits.\n\nThe Ioff feature disables outputs when VCC is at 0 V, preventing damaging backflow current in partial-power-down and live-insertion applications. The \u00b124-mA output drive at 3.3 V (\u00b132 mA at 5 V) can directly drive LED indicators or interface with TTL-level inputs. The 10-\u00b5A maximum ICC makes the device suitable for always-on logic circuits.\n\nThe VSSOP-8 (DCU) package occupies only 4.6 mm\u00b2 of board area, approximately half the size of the SSOP-8 (DCT) alternative. TI also offers a DSBGA (chip-scale) package (YZP suffix) at 1.91\u00d70.91 mm for ultra-compact designs. The -40\u00b0C to +125\u00b0C operating range (DCUR suffix) supports automotive and industrial applications.","working_principle":"**D Flip-Flop Core:** The SN74LVC2G74 uses CMOS transmission-gate and inverter-based master-slave latch architecture. On the low phase of CLK, the master latch is transparent and tracks the D input. On the rising edge of CLK, the master latch closes and the slave latch opens, transferring the captured D value to the Q output. This edge-triggered behavior ensures that Q changes only once per clock cycle.\n\n**Asynchronous Preset and Clear:** The PRE and CLR inputs bypass the clocked path. When PRE is low, an internal pull-up path forces Q high regardless of CLK and D. When CLR is low, an internal pull-down path forces Q low. Both inputs are level-sensitive and active-low. If both PRE and CLR are asserted simultaneously, both Q and Q-bar go high (invalid state); the last one released determines the final output.\n\n**Ioff Partial Power-Down:** When VCC = 0 V, the Ioff circuitry places all I\/O pins in a high-impedance state. This prevents current from flowing from an external signal (e.g., from a powered device on the same bus) through the SN74LVC2G74's internal ESD diodes to the unpowered VCC rail. This is critical for hot-swap and battery-backup systems where some devices may be powered while others are not.\n\n**Wide-Voltage Operation:** The LVC architecture uses a thin-oxide CMOS process that supports 1.65-V to 5.5-V operation. Input pins accept voltages up to 5.5 V independently of VCC, allowing the device to translate between voltage domains (e.g., 3.3-V input signals with 1.8-V VCC).","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | CLK<\/td> | I<\/td> | Clock input; positive-edge triggered; data at D is captured on rising edge; triggering at voltage level, not rise time<\/td><\/tr> | ||||||||||||||||||||||||||||
| 2<\/td> | D<\/td> | I<\/td> | Data input; must meet setup time (1.1ns min at 5V) before CLK rising edge and hold time (500ps) after<\/td><\/tr> | ||||||||||||||||||||||||||||
| 3<\/td> | Q<\/td> | O<\/td> | True output; reflects D value captured on CLK rising edge; \u00b124mA drive at 3.3V<\/td><\/tr> | ||||||||||||||||||||||||||||
| 4<\/td> | GND<\/td> | G<\/td> | Ground; connect to PCB ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||
| 5<\/td> | Q-bar<\/td> | O<\/td> | Complementary output; inverted Q; \u00b124mA drive; both Q and Q-bar available simultaneously<\/td><\/tr> | ||||||||||||||||||||||||||||
| 6<\/td> | CLR<\/td> | I<\/td> | Asynchronous clear (active low); forces Q low and Q-bar high when asserted; overrides CLK and D; do not leave floating<\/td><\/tr> | ||||||||||||||||||||||||||||
| 7<\/td> | PRE<\/td> | I<\/td> | Asynchronous preset (active low); forces Q high and Q-bar low when asserted; overrides CLK and D; do not leave floating<\/td><\/tr> | ||||||||||||||||||||||||||||
| 8<\/td> | VCC<\/td> | P<\/td> | Supply voltage 1.65-5.5V; bypass with 0.1\u00b5F ceramic to GND<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|