The TXS0102DCUR from Texas Instruments is a 2-bit bidirectional voltage-level translator for open-drain and push-pull applications in an 8-pin VSSOP (DCU) package. It supports A-port voltages from 1.65 V to 3.6 V (VCCA) and B-port voltages from 2.3 V to 5.5 V (VCCB), enabling translation between 1.8-V, 2.5-V, 3.3-V, and 5-V logic nodes without direction control. Maximum data rates are 24 Mbps (push-pull) and 2 Mbps (open-drain). Features include VCC isolation, partial-power-down Ioff support, no power-supply sequencing requirement, and ESD protection up to 8-kV HBM on the B port. Operating temperature range is -40\u00b0C to +85\u00b0C.<\/p>","protected":false},"excerpt":{"rendered":"
The TXS0102DCUR from Texas Instruments is a 2-bit bidirectional voltage-level translator for open-drain and push-pull applications in an 8-pin VSSOP (DCU) package. It supports A-port voltages from 1.65 V to 3.6 V (VCCA) and B-port voltages from 2.3 V to 5.5 V (VCCB), enabling translation between 1.8-V, 2.5-V, 3.3-V, and 5-V logic nodes without direction […]<\/p>\n","protected":false},"author":2,"featured_media":2872,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-2036","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"2-bit bi-dir level shifter, 1.65-3.6V A \/ 2.3-5.5V B, 24Mbps push-pull, auto-direction, VSSOP-8, -40~85\u00b0C","date_code":"","package_case":"VSSOP-8 (DCU) (2.3 x 2.0 x 0.9 mm, 0.5mm pitch)","in_stock":8000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/txs0102.pdf","price":"$0.38 (1K+ pcs)","product_introduction":"The TXS0102DCUR is a 2-bit bidirectional voltage-level translator from Texas Instruments designed for mixed-voltage systems where I\u00b2C, UART, GPIO, or other digital signals must cross between different voltage domains. It requires no direction-control signal \u2014 each channel automatically senses and translates in both directions, simplifying board design.\n\nThe A port operates from 1.65 V to 3.6 V (tracking VCCA), and the B port operates from 2.3 V to 5.5 V (tracking VCCB), with the constraint VCCA \u2264 VCCB. This covers all common logic voltage combinations: 1.8 V-to-3.3 V, 1.8 V-to-5 V, 3.3 V-to-5 V, and 2.5 V-to-3.3 V.\n\nThe TXS architecture uses passive pass-transistor switches with edge-rate accelerators. For open-drain buses (I\u00b2C, SMBus), the pass-FET provides a low-impedance path and the one-shot accelerator briefly turns on a strong pull-up to speed rising edges, achieving up to 2 Mbps. For push-pull signals (UART, SPI, GPIO), the accelerator provides fast edges up to 24 Mbps.\n\nThe VCC isolation feature ensures that if either VCCA or VCCB is at GND, both ports enter a high-impedance state, preventing back-feeding. The Ioff circuitry supports partial-power-down mode, allowing one side to be powered down while the other remains active without leakage. No power-supply sequencing is required \u2014 either rail can ramp first.\n\nESD protection is asymmetric: the A port provides 2.5-kV HBM, while the B port (facing the higher-voltage, often external-facing side) provides 8-kV HBM. The OE pin, when pulled low, places all I\/Os in high-impedance state with reduced quiescent current. The VSSOP-8 (DCU) package occupies only 4.6 mm\u00b2 of board area, making it ideal for space-constrained portable designs.","working_principle":"**Pass-FET Switch Core:** Each channel consists of an N-channel pass transistor connecting the A and B sides. The pass-FET gate is biased at a voltage between VCCA and VCCB, allowing bidirectional current flow when either side drives low. The on-resistance is approximately 10 \u03a9, providing a low-impedance path for DC and low-frequency signals.\n\n**Edge-Rate Accelerator:** One-shot circuits on each side detect falling edges and briefly turn on a strong pull-down (\u2248 30 mA for ~30 ns) to accelerate the transition. For rising edges on open-drain buses, the accelerator briefly turns on a strong pull-up to overcome the weak external pull-up resistor. This enables 2 Mbps on I\u00b2C at 3.3-V\/5-V translation.\n\n**Auto-Direction Detection:** The TXS translator has no explicit direction control. The pass-FET inherently allows either side to drive the bus low. When neither side is driving, the external pull-up resistors (for open-drain) or the driving device (for push-pull) pull the line high through the pass-FET. This transparent operation eliminates the need for a DIR pin.\n\n**VCC Isolation and Ioff:** When either supply is at GND, an internal circuit detects the condition and opens the pass-FET, placing both I\/Os in high-impedance. The Ioff feature ensures that no leakage current flows from the powered side to the unpowered side, which is critical for hot-swap and battery-backup applications.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | VCCA<\/td> | P<\/td> | A-port supply (1.65-3.6V); powers A-side I\/O buffers and OE input logic; bypass with 0.1\u00b5F ceramic to GND<\/td><\/tr> | ||||||||||||||||||||||||||||
| 2<\/td> | A1<\/td> | I\/O<\/td> | Channel 1 A-port I\/O; voltage referenced to VCCA; connects to low-voltage side of signal<\/td><\/tr> | ||||||||||||||||||||||||||||
| 3<\/td> | A2<\/td> | I\/O<\/td> | Channel 2 A-port I\/O; voltage referenced to VCCA<\/td><\/tr> | ||||||||||||||||||||||||||||
| 4<\/td> | GND<\/td> | G<\/td> | Ground; connect to PCB ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||
| 5<\/td> | B2<\/td> | I\/O<\/td> | Channel 2 B-port I\/O; voltage referenced to VCCB; connects to high-voltage side of signal<\/td><\/tr> | ||||||||||||||||||||||||||||
| 6<\/td> | B1<\/td> | I\/O<\/td> | Channel 1 B-port I\/O; voltage referenced to VCCB<\/td><\/tr> | ||||||||||||||||||||||||||||
| 7<\/td> | VCCB<\/td> | P<\/td> | B-port supply (2.3-5.5V); powers B-side I\/O buffers; must be \u2265 VCCA; bypass with 0.1\u00b5F ceramic to GND<\/td><\/tr> | ||||||||||||||||||||||||||||
| 8<\/td> | OE<\/td> | I<\/td> | Output enable (active high); referenced to VCCA; tie to GND via pull-down resistor for safe power-up; internal pull-up to VCCA; pull low to disable all I\/Os (Hi-Z)<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
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