\u0625\u0646 AR8031-AL1B AR8031-AL1B \u0645\u0646 Qualcomm (\u0627\u0644\u0645\u0639\u0631\u0648\u0641\u0629 \u0633\u0627\u0628\u0642\u064b\u0627 \u0628\u0627\u0633\u0645 Atheros Communications) \u0647\u0648 \u062c\u0647\u0627\u0632 \u0625\u064a\u062b\u0631\u0646\u062a \u0645\u0646 \u0627\u0644\u062c\u064a\u0644 \u0627\u0644\u0631\u0627\u0628\u0639 \u0623\u062d\u0627\u062f\u064a \u0627\u0644\u0645\u0646\u0641\u0630 10\/100\/1000 \u0645\u064a\u062c\u0627 \u0628\u062a \u0641\u064a \u0627\u0644\u062b\u0627\u0646\u064a\u0629 \u062b\u0644\u0627\u062b\u064a \u0627\u0644\u0633\u0631\u0639\u0629 (\u062c\u0647\u0627\u0632 \u0625\u0631\u0633\u0627\u0644 \u0648\u0627\u0633\u062a\u0642\u0628\u0627\u0644 \u0625\u064a\u062b\u0631\u0646\u062a \u062b\u0644\u0627\u062b\u064a \u0627\u0644\u0633\u0631\u0639\u0629) \u0641\u064a \u062d\u0632\u0645\u0629 \u0644\u0648\u062d\u0629 \u0645\u0643\u0634\u0648\u0641\u0629 QFN \u0630\u0627\u062a 6 \u00d7 6 \u0645\u0645 \u0645\u0642\u0627\u0633 48 \u0633\u0646\u064b\u0627 QFN. \u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629: \u0645\u062a\u0648\u0627\u0641\u0642 \u0645\u0639 IEEE 802.3 (10BASE-T \u0648100BASE-TX \u06481000BASE-T)\u061b \u0648\u0627\u062c\u0647\u0627\u062a RGMII \u0648SGMII MAC\u061b \u0633\u064a\u0631\u062f\u064a\u0633 \u0645\u062f\u0645\u062c \u064a\u062f\u0639\u0645 1000BASE-X \u0648100BASE-FX \u0627\u0644\u0644\u064a\u0641\u064a\u0629\u061b \u062f\u0639\u0645 IEEE 802.3az Ethernet \u0627\u0644\u0645\u0648\u0641\u0631 \u0644\u0644\u0637\u0627\u0642\u0629 (EEE)\u061b SmartEEE \u0644\u0623\u062c\u0647\u0632\u0629 MAC\/SoC \u0627\u0644\u0642\u062f\u064a\u0645\u0629\u061b \u062f\u0639\u0645 IEEE 1588v2 \u0648IEEE 1588v2 \u0648Synchronous Ethernet\u061b \u0627\u0644\u0627\u0633\u062a\u064a\u0642\u0627\u0638 \u0639\u0644\u0649 \u0627\u0644\u0634\u0628\u0643\u0629 (WoL)\u061b \u062a\u0642\u0646\u064a\u0629 \u062a\u0648\u0641\u064a\u0631 \u0627\u0644\u0637\u0627\u0642\u0629 ETHOS \u0627\u0644\u062e\u0636\u0631\u0627\u0621 \u0645\u0646 Atheros\u061b \u0645\u0635\u062f\u0631 \u0637\u0627\u0642\u0629 \u0648\u0627\u062d\u062f 3.3 \u0641\u0648\u0644\u062a\u061b \u062a\u064a\u0627\u0631 \u0627\u0644\u0625\u0645\u062f\u0627\u062f 113.7 \u0645\u0644\u0644\u064a \u0623\u0645\u0628\u064a\u0631 \u0643\u062d\u062f \u0623\u0642\u0635\u0649\u061b \u0645\u0639\u062f\u0644 \u0628\u064a\u0627\u0646\u0627\u062a \u064a\u0635\u0644 \u0625\u0644\u0649 1 \u062c\u064a\u062c\u0627\u0628\u062a \u0641\u064a \u0627\u0644\u062b\u0627\u0646\u064a\u0629\u061b \u0645\u0642\u0627\u0648\u0645\u0627\u062a \u0625\u0646\u0647\u0627\u0621 MDI \u0645\u062f\u0645\u062c\u0629\u061b \u0645\u0639\u0627\u062f\u0644\u0627\u062a \u0631\u0642\u0645\u064a\u0629 \u062a\u0643\u064a\u0641\u064a\u0629 \u0645\u062f\u0645\u062c\u0629 \u0648\u0623\u062c\u0647\u0632\u0629 \u0625\u0644\u063a\u0627\u0621 \u0627\u0644\u0635\u062f\u0649 \u0648\u0623\u062c\u0647\u0632\u0629 \u0625\u0644\u063a\u0627\u0621 \u0627\u0644\u0635\u062f\u0649 \u0648\u0623\u062c\u0647\u0632\u0629 \u0625\u0644\u063a\u0627\u0621 \u0627\u0644\u062a\u0627\u0644\u064a\u061b \u0627\u0644\u062a\u062d\u0648\u064a\u0644 \u0627\u0644\u062a\u0644\u0642\u0627\u0626\u064a \u0644\u0640 MDI\/MDIX \u0648\u062a\u0635\u062d\u064a\u062d \u0627\u0644\u0642\u0637\u0628\u064a\u0629\u061b \u0627\u0644\u062a\u0628\u062f\u064a\u0644 \u0627\u0644\u062a\u0644\u0642\u0627\u0626\u064a \u0644\u0644\u0642\u0646\u0648\u0627\u062a (ACS)\u061b \u0627\u062e\u062a\u0628\u0627\u0631 \u062a\u0634\u062e\u064a\u0635 \u0627\u0644\u0643\u0627\u0628\u0644 (CDT)\u061b \u0623\u0648\u0636\u0627\u0639 \u0627\u0644\u0627\u0633\u062a\u0631\u062c\u0627\u0639 \u0627\u0644\u0645\u062a\u0639\u062f\u062f\u0629; \u062d\u0645\u0627\u064a\u0629 \u0645\u0646 \u062d\u062f\u062b \u062a\u0641\u0631\u064a\u063a \u0627\u0644\u0643\u0627\u0628\u0644 (CDE) \u0632\u0627\u0626\u062f \u0623\u0648 \u0646\u0627\u0642\u0635 6 \u0643\u064a\u0644\u0648 \u0641\u0648\u0644\u062a\u061b \u062d\u0645\u0627\u064a\u0629 \u0645\u0646 \u0632\u064a\u0627\u062f\u0629 \u0627\u0644\u062a\u064a\u0627\u0631 \u0632\u0627\u0626\u062f \u0623\u0648 \u0646\u0627\u0642\u0635 750 \u0641\u0648\u0644\u062a \u0641\u064a \u0627\u0644\u0648\u0636\u0639 \u0627\u0644\u062a\u0641\u0627\u0636\u0644\u064a \u0632\u0627\u0626\u062f \u0623\u0648 \u0646\u0627\u0642\u0635 750 \u0641\u0648\u0644\u062a \u0632\u0627\u0626\u062f \u0623\u0648 \u0646\u0627\u0642\u0635 4 \u0643\u064a\u0644\u0648 \u0641\u0648\u0644\u062a \u0641\u064a \u0627\u0644\u0648\u0636\u0639 \u0627\u0644\u0645\u0634\u062a\u0631\u0643\u061b \u062f\u0639\u0645 \u0625\u0637\u0627\u0631 \u062c\u0627\u0645\u0628\u0648 \u064a\u0635\u0644 \u0625\u0644\u0649 10 \u0643\u064a\u0644\u0648\u0628\u0627\u064a\u062a\u061b \u0643\u0627\u0628\u0644 \u0645\u0645\u062a\u062f \u064a\u0635\u0644 \u0625\u0644\u0649 140 \u0645\u062a\u0631 CAT5\u061b \u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644 -40 \u0625\u0644\u0649 +85 \u062f\u0631\u062c\u0629 \u0645\u0626\u0648\u064a\u0629 (\u062f\u0631\u062c\u0629 \u0635\u0646\u0627\u0639\u064a\u0629). \u062a\u0634\u064a\u0631 \u0644\u0627\u062d\u0642\u0629 AL1B \u0625\u0644\u0649 48 \u0633\u0646\u064b\u0627 QFN EP \u0630\u0627\u062a 48 \u0633\u0646\u064b\u0627 \u0645\u0639 \u062a\u063a\u0644\u064a\u0641 \u0635\u064a\u0646\u064a\u0629. \u062a\u0645 \u0646\u0642\u0644 \u062d\u0627\u0644\u0629 \u0627\u0644\u0645\u0646\u062a\u062c \u0645\u0646 Atheros \u0625\u0644\u0649 Qualcomm.<\/p>","protected":false},"excerpt":{"rendered":"
The AR8031-AL1B from Qualcomm (formerly Atheros Communications) is a fourth-generation single-port 10\/100\/1000 Mbps tri-speed Ethernet PHY (Physical Layer Transceiver) in a 6 x 6 mm 48-pin QFN exposed pad package. Key specifications: IEEE 802.3 compliant (10BASE-T, 100BASE-TX, 1000BASE-T); RGMII and SGMII MAC interfaces; integrated SerDes supporting 1000BASE-X and 100BASE-FX fiber; IEEE 802.3az Energy Efficient Ethernet […]<\/p>\n","protected":false},"author":2,"featured_media":2900,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[21,13],"tags":[],"chip_brand":[158],"class_list":["post-1969","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-audio-ics","category-integrated-circuits-ics","chip_brand-realtek"],"acf":{"brief_explanation":"10\/100\/1000Mbps Ethernet PHY, RGMII\/SGMII, 802.3az EEE, 1588v2, WoL, Green ETHOS, 3.3V, QFN-48 6x6mm, -40~85C","date_code":"","package_case":"QFN-48 EP (6 x 6 x 0.8 mm, 0.4mm pitch)","in_stock":8000,"datasheet":"https:\/\/www.qualcomm.com\/products\/technology\/processors\/connectivity\/ar8031","price":"$5.48 (1K+ pcs)","product_introduction":"The AR8031-AL1B from Qualcomm (originally developed by Atheros Communications, later acquired by Qualcomm) is a fourth-generation single-port Gigabit Ethernet PHY transceiver that provides 10\/100\/1000 Mbps copper and fiber Ethernet connectivity. It is one of the most widely used Gigabit Ethernet PHYs in embedded networking, enterprise equipment, and consumer devices.\n\nThe AR8031 supports both RGMII (Reduced Gigabit Media Independent Interface) and SGMII (Serial Gigabit Media Independent Interface) connections to the MAC layer, making it compatible with virtually all modern Ethernet-capable processors, SoCs, and switch ASICs. The RGMII interface is the most common for embedded processors (NXP i.MX, TI Sitara, Xilinx Zynq, etc.), while SGMII is used for higher-density switch and router designs.\n\nThe integrated SerDes allows the AR8031 to support fiber interfaces (1000BASE-X and 100BASE-FX) in addition to copper (1000BASE-T, 100BASE-TX, 10BASE-T). This copper-fiber combo mode enables SFP module connections and media converter applications without requiring an external SerDes chip.\n\nThe IEEE 802.3az Energy Efficient Ethernet (EEE) support significantly reduces power consumption during periods of low data utilization by entering a low-power idle (LPI) state between frames. The SmartEEE feature extends EEE benefits to systems with MAC\/SoC devices that do not natively support 802.3az, by autonomously managing the LPI state transitions within the PHY itself.\n\nThe Atheros Green ETHOS power saving technology goes beyond EEE by dynamically adjusting the DSP processing power based on the actual cable length. Shorter cables require less equalization and echo cancellation, allowing the PHY to reduce DSP power consumption automatically. This cable-length-adaptive power saving can reduce 1000BASE-T power consumption by up to 40 percent on short cables compared to conventional PHYs.\n\nThe IEEE 1588v2 and Synchronous Ethernet support makes the AR8031 suitable for time-sensitive networking applications that require precise clock synchronization, such as telecommunications base stations, industrial automation, and financial trading systems. The recovered clock output allows the PHY to serve as a timing reference for the system.\n\nThe integrated MDI termination resistors simplify the PCB design by eliminating 8 external resistor components that would otherwise be required between the PHY and the RJ-45 connector\/magnetics. This reduces BOM cost and PCB area while improving signal integrity.\n\nThe cable diagnostic test (CDT) feature allows the system to detect and report cable faults (open, short, impedance mismatch) and estimate the distance to the fault, enabling remote troubleshooting without physical inspection.\n\nThe AR8031-AL1B is widely used in embedded Linux platforms (NXP i.MX6\/i.MX8, TI AM335x\/AM572x, Xilinx Zynq) with mainline Linux kernel driver support. The device is managed through an MDIO (MDC\/MDIO) interface and configurable via register settings and strap options at power-up.","working_principle":"The AR8031-AL1B operates as the physical layer (PHY) transceiver in an Ethernet system, implementing the IEEE 802.3 physical layer functions to transmit and receive data over twisted-pair copper cable or fiber optic media.\n\nPhysical Coding Sublayer (PCS): The PCS handles the encoding and decoding of Ethernet frames for transmission over the physical medium. For 1000BASE-T, the PCS implements 4D-PAM5 (4-dimensional, 5-level pulse amplitude modulation) encoding, where 2 bits are encoded per symbol on each of the 4 wire pairs, achieving 1000 Mbps data throughput. For 100BASE-TX, the PCS implements 4B\/5B encoding with MLT-3 signaling. For 10BASE-T, the PCS implements Manchester encoding.\n\nPhysical Medium Attachment (PMA): The PMA sublayer performs the analog front-end functions including the DAC (digital-to-analog converter) for transmission, the ADC (analog-to-digital converter) for reception, and the hybrid circuit that separates transmit and receive signals on the same wire pair (for 1000BASE-T full-duplex operation where all four pairs carry simultaneous bidirectional traffic).\n\nEcho Cancellation and NEXT Cancellation: In 1000BASE-T full-duplex mode, all four pairs carry simultaneous transmit and receive signals. The AR8031 uses fully integrated digital adaptive equalizers, echo cancellers, and near-end crosstalk (NEXT) cancellers to separate the desired received signal from the transmitted signal (echo) and crosstalk from adjacent pairs. The echo canceller models the transmit-to-receive leakage path and subtracts the estimated echo from the received signal. The NEXT cancellers similarly model the crosstalk coupling between pairs and subtract the estimated crosstalk. These adaptive filters continuously update their coefficients during normal operation to track changes in cable characteristics and temperature.\n\nAuto-Negotiation: The AR8031 implements IEEE 802.3u auto-negotiation to automatically determine the highest common speed and duplex setting with the link partner. During auto-negotiation, the PHY exchanges Fast Link Pulse (FLP) bursts that advertise its capabilities (10\/100\/1000 Mbps, half\/full duplex, EEE, etc.). The highest common denominator is selected. The AR8031 also supports next-page functionality for 1000BASE-T auto-negotiation.\n\nRGMII\/SGMII MAC Interface: The MAC interface carries the Ethernet data between the PHY and the MAC layer in the processor or switch. In RGMII mode, the data is transferred on a 12-pin interface (TXD[3:0], TXC, TX_CTL, RXD[3:0], RXC, RX_CTL) at 125 MHz clock rate for 1000 Mbps operation. The RGMII supports both internal and external delay modes on the RX path to meet timing requirements. In SGMII mode, the data is transferred on a 2-pin differential serial interface (RX_p\/n, TX_p\/n) at 1.25 Gbaud, which is more pin-efficient for multi-port designs.\n\nSerDes and Fiber Interface: The integrated SerDes (Serializer\/Deserializer) provides a 1000BASE-X or 100BASE-FX fiber interface. In 1000BASE-X mode, the SerDes operates at 1.25 Gbaud using 8B\/10B encoding, suitable for direct connection to SFP optical transceiver modules. The fiber mode is selected through MDIO register configuration or hardware strap options.\n\nEnergy Efficient Ethernet (EEE): The AR8031 supports IEEE 802.3az EEE, which reduces power consumption during periods of low link utilization. When EEE is active and there is no data to transmit, the PHY enters a low-power idle (LPI) state where the transmitter is turned off and the receiver operates in a reduced-power mode. The PHY periodically sends refresh signals to maintain the link partner's equalizer adaptation. When data needs to be transmitted, the PHY exits LPI and resumes normal operation within a few microseconds.\n\nIEEE 1588v2 PTP: The AR8031 supports the Precision Time Protocol (PTP) defined by IEEE 1588v2, which enables sub-microsecond clock synchronization between network nodes. The PHY can timestamp the arrival and departure of PTP packets with nanosecond precision, enabling accurate time synchronization for industrial automation, telecommunications, and financial applications.\n\nCable Diagnostics: The cable diagnostic test (CDT) feature uses time-domain reflectometry (TDR) to analyze the cable characteristics. By transmitting a test pulse and measuring the reflected signal, the PHY can determine the cable length, detect open circuits, short circuits, and impedance mismatches, and estimate the distance to any faults.","pin_description":"
| Pin Group<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MDIO Interface<\/td> | MDC, MDIO<\/td> | Control<\/td> | MDIO management interface for register access; MDC clock input up to 12.5 MHz; MDIO bidirectional data; Clause 22 protocol with PHY address set by strap pins; used for configuration, status monitoring, and diagnostics; MDC is driven by the MAC\/SoC; MDIO requires 4.7 kOhm external pull-up<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| RGMII Interface<\/td> | TXD[3:0], TXC, TX_CTL, RXD[3:0], RXC, RX_CTL<\/td> | Digital I\/O<\/td> | RGMII MAC interface for 10\/100\/1000 Mbps data transfer; TXD[3:0] and TXC carry transmit data at 125 MHz for 1000 Mbps; RXD[3:0] and RXC carry receive data; TX_CTL and RX_CTL indicate valid data and error conditions; 2.5 V or 3.3 V I\/O voltage (set by strap or register); supports internal RX delay (1.5-2.0 ns) and external delay modes<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| SGMII Interface<\/td> | SGMII_TX_p\/n, SGMII_RX_p\/n<\/td> | Differential I\/O<\/td> | SGMII MAC interface for serial Gigabit data transfer; differential 1.25 Gbaud signaling; pin-efficient alternative to RGMII (2 pairs vs 12 pins); AC coupled with 0.1 uF capacitors; selected via strap or register; used primarily in switch and router ASIC connections<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| MDI Interface<\/td> | TXP_0\/TXN_0 through TXP_3\/TXN_3, RXP_0\/RXN_0 through RXP_3\/RXN_3<\/td> | Analog I\/O<\/td> | Media Dependent Interface for connection to magnetics\/RJ-45; 4 differential pairs for 1000BASE-T; integrated 50 Ohm MDI termination resistors (no external resistors needed); connect through Ethernet magnetics (1:1 ratio) to RJ-45 connector; cable discharge event (CDE) protection plus or minus 6 kV<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| SerDes Fiber<\/td> | SD_TX_p\/n, SD_RX_p\/n<\/td> | Differential I\/O<\/td> | 1000BASE-X \/ 100BASE-FX SerDes interface for fiber connection; 1.25 Gbaud for 1000BASE-X; AC coupled; can connect directly to SFP module; selected via strap or register; fiber mode supports automatic failover to copper (combo mode)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Power<\/td> | VDD33, VDDIO, GND<\/td> | Power<\/td> | VDD33: 3.3 V analog and digital power supply; VDDIO: 2.5 V or 3.3 V I\/O supply for RGMII (selectable); GND: ground connections; multiple VDD33 and GND pins must all be connected; bypass each VDD33 pin with 100 nF ceramic capacitor; add 10 uF bulk capacitor near the device<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Configuration<\/td> | STRAP pins<\/td> | Input<\/td> | Multiple strap pins set the initial configuration at power-up (PHY address, MAC interface mode, RGMII voltage, LED configuration, etc.); each strap pin has an internal pull-up or pull-down; external resistor or direct connection to VDD\/GND selects the desired option; values are latched at power-on reset<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Pin Group<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
| Clock<\/td> | XTAL_IN, XTAL_OUT<\/td> | Analog I\/O<\/td> | Crystal oscillator or external clock input; connect a 25 MHz crystal (20 ppm) with load capacitors; alternatively, apply a 25 MHz clock signal to XTAL_IN and leave XTAL_OUT unconnected; the 25 MHz reference is multiplied internally by PLL to generate the required sampling and serialization clocks<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| LED<\/td> | LED[2:0]<\/td> | Output<\/td> | LED outputs for link\/activity\/speed indication; directly drive LED through current-limiting resistor; LED behavior is configurable via MDIO registers; active-low output; can indicate 10\/100\/1000 link speed, activity, duplex, and collision<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Interrupt<\/td> | INT<\/td> | Output<\/td> | Interrupt output to MAC\/SoC; active-low open-drain; asserts on link status change, auto-negotiation completion, energy detect, WoL, and error conditions; requires external pull-up resistor; maskable via MDIO registers<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Reset<\/td> | RST_N<\/td> | Input<\/td> | Active-low hardware reset; pull low for minimum 10 ms to reset the PHY; internal pull-up with debounce; all registers return to default (or strap-selected) values; must be asserted after power-on to ensure reliable initialization<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|