The TUSB9261PVP from Texas Instruments is a USB 3.0 (5 Gbps) to Serial ATA (SATA) bridge controller with an integrated ARM Cortex-M3 core, in a 64-pin HTQFP package (9 x 9 x 1.4 mm). Key specifications: USB SuperSpeed 5 Gbps compliant (TID 340730020) with integrated transceiver supporting SS\/HS\/FS signaling; SATA Specification Revision 2.6 supporting Gen1i (1.5 Gbps), Gen1m, Gen2i (3.0 Gbps), and Gen2m signaling; integrated ARM Cortex-M3 microcontroller core; USB Attached SCSI Protocol (UASP) support for high-performance mass storage; USB Mass Storage Class Bulk-Only Transport (BOT); USB Human Interface Device (HID) class support; USB bootability support; firmware update via USB using TI-provided application; support for HDD, SSD, optical drives, and other ATA\/ATAPI-8 compatible devices; best-in-class adaptive equalizer for USB receiver jitter tolerance; customizable application code loaded from external EEPROM via SPI interface; two additional SPI chip selects for peripheral connection; up to 12 GPIOs for end-user configuration; two GPIOs with PWM functionality for LED blink speed control; UART debug interface; integrated spread spectrum clock generation from single 40 MHz crystal or clock oscillator; JTAG interface for IEEE 1149.1 and 1149.6 boundary scan; dual supply voltages 1.1 V and 3.3 V; operating temperature -40 to +85 degrees C. RoHS compliant. HTQFP-64 (PVP) package.<\/p>","protected":false},"excerpt":{"rendered":"
The TUSB9261PVP from Texas Instruments is a USB 3.0 (5 Gbps) to Serial ATA (SATA) bridge controller with an integrated ARM Cortex-M3 core, in a 64-pin HTQFP package (9 x 9 x 1.4 mm). Key specifications: USB SuperSpeed 5 Gbps compliant (TID 340730020) with integrated transceiver supporting SS\/HS\/FS signaling; SATA Specification Revision 2.6 supporting Gen1i […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,15],"tags":[],"chip_brand":[138],"class_list":["post-1944","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-logic-chips","chip_brand-ti"],"acf":{"brief_explanation":"USB 3.0 5Gbps to SATA 3Gbps bridge, ARM Cortex-M3, UASP\/BOT\/HID, SPI EEPROM, 12 GPIO, 2 PWM LED, UART debug, HTQFP-64, 1.1V+3.3V, -40~85C","date_code":"","package_case":"HTQFP-64 (PVP) (9 x 9 x 1.4 mm, 0.5mm pitch)","in_stock":3000,"datasheet":"https:\/\/www.ti.com\/product\/TUSB9261","price":"$7.50 (1K+ pcs)","product_introduction":"The TUSB9261PVP from Texas Instruments is a fully integrated USB 3.0 to SATA bridge controller that enables the design of external hard disk drives, solid-state drives, and optical drive enclosures with a single-chip solution. It bridges the SuperSpeed USB 3.0 bus (5 Gbps) to the Serial ATA bus (up to 3 Gbps, SATA Gen2), providing the hardware and firmware to implement a complete mass storage device.\n\nThe TUSB9261 is built around an integrated ARM Cortex-M3 microcontroller core that runs the bridge firmware. The firmware implements the USB Attached SCSI Protocol (UASP), which provides significantly higher throughput than the legacy USB Mass Storage Class Bulk-Only Transport (BOT) protocol. UASP eliminates the command queueing bottleneck of BOT by allowing multiple commands to be outstanding simultaneously, enabling the drive to process commands out of order and overlap data transfers. With UASP and USB 3.0, the TUSB9261 can achieve sustained data transfer rates exceeding 200 MB\/s with a SATA Gen2 SSD, compared to approximately 40 MB\/s with BOT over USB 2.0.\n\nThe USB interface supports SuperSpeed (5 Gbps), High-Speed (480 Mbps), and Full-Speed (12 Mbps) signaling, providing backward compatibility with USB 2.0 and USB 1.1 hosts. The integrated SuperSpeed transceiver eliminates the need for an external USB 3.0 PHY. The best-in-class adaptive equalizer in the USB receiver provides superior jitter tolerance, enabling reliable operation with longer cables and lower-quality signal paths.\n\nThe SATA interface supports all Gen1 (1.5 Gbps) and Gen2 (3.0 Gbps) signaling rates, as well as the Gen1m and Gen2m spread-spectrum signaling modes. It is compatible with the ATA\/ATAPI-8 specification, supporting HDDs, SSDs, optical drives (CD\/DVD\/Blu-ray), and other SATA mass-storage devices.\n\nThe firmware is stored in an external SPI EEPROM and loaded into internal SRAM at power-up. This allows the firmware to be updated in the field via USB using a TI-provided application, enabling bug fixes and feature additions without hardware changes. The SPI interface also provides two additional chip selects (SPI_CS1 and SPI_CS2) that can be used to connect peripheral devices such as a second EEPROM, a security chip, or a configuration register.\n\nUp to 12 GPIO pins provide flexibility for product differentiation. Two of the GPIO pins include PWM functionality that can drive activity LEDs with configurable blink rates, eliminating the need for external LED driver circuitry. The remaining GPIOs can be used for product-specific functions such as write-protect switches, power control, or configuration strapping.\n\nThe UART debug interface provides a serial console for development and troubleshooting. The JTAG interface supports IEEE 1149.1 boundary scan for manufacturing test and IEEE 1149.6 for AC testing of the differential USB and SATA signals.\n\nThe integrated spread spectrum clock generation (SSCG) allows operation from a single low-cost 40 MHz crystal or clock oscillator, reducing BOM cost. The SSCG modulates the clock frequency slightly to spread the EMI energy across a wider bandwidth, helping the product pass FCC\/CISPR emissions testing.\n\nThe PVP suffix denotes the HTQFP-64 (Heat-sink Thin Quad Flat Pack) package with 0.5 mm pitch. The device requires two supply voltages: 1.1 V (core and USB\/SATA PHY) and 3.3 V (I\/O). An external voltage regulator is typically used to generate the 1.1 V supply from the 3.3 V or 5 V input.\n\nImportant note: The default TI firmware and reference design have the SATA TXP\/TXM signals swapped for ease of PCB routing. Designers using the TI default firmware must review the reference design in the TUSB9261 DEMO User's Guide (SLLU139) for proper SATA connection.","working_principle":"The TUSB9261PVP operates as a USB 3.0 to SATA protocol bridge with an integrated ARM Cortex-M3 controller managing all data transfers and protocol conversion.\n\nARM Cortex-M3 Core: The on-chip Cortex-M3 core runs the bridge firmware that handles all USB and SATA protocol processing, command translation, data management, and error handling. The firmware is loaded from an external SPI EEPROM into internal SRAM at power-up. The firmware implements multiple USB device class interfaces simultaneously: UASP (for high-performance data transfer), BOT (for legacy compatibility), and HID (for firmware updates and device configuration).\n\nUSB 3.0 SuperSpeed Operation: The USB 3.0 interface operates at 5 Gbps using two differential signal pairs: one for transmit (USB_SSTXP\/M) and one for receive (USB_SSRXP\/M). The USB 3.0 protocol uses separate unidirectional paths for upstream and downstream data, enabling simultaneous bidirectional communication. The TUSB9261 implements the USB Mass Storage Device (MSD) function using UASP, which supports up to 65535 queued commands per LUN with command completion notification. The adaptive equalizer in the receiver automatically adjusts to compensate for signal degradation from cable loss, ensuring reliable data reception.\n\nUSB 2.0 Backward Compatibility: In addition to SuperSpeed, the TUSB9261 supports USB 2.0 High-Speed (480 Mbps) and Full-Speed (12 Mbps) operation through the USB_DP\/DM pins. When connected to a USB 2.0 host, the device automatically falls back to High-Speed or Full-Speed operation using the BOT protocol (UASP is not supported over USB 2.0). This backward compatibility is automatic and requires no firmware intervention.\n\nSATA Operation: The SATA interface operates at Gen1 (1.5 Gbps) or Gen2 (3.0 Gbps) using differential transmit (SATA_TXP\/M) and receive (SATA_RXP\/M) pairs. The TUSB9261 implements the Serial ATA protocol including FIS (Frame Information Structure) generation and parsing, DMA setup, and data management for both read and write operations. The SATA link speed is auto-negotiated with the connected device.\n\nProtocol Translation: The firmware translates USB mass storage commands (SCSI commands encapsulated in UASP or BOT) to SATA\/ATA commands. For example, a SCSI READ(10) command from the USB host is translated to an ATA READ DMA command on the SATA bus. The firmware manages the data buffers, handles command queuing, and manages error recovery between the two buses.\n\nClock Architecture: The 40 MHz reference clock is provided by an external crystal or oscillator connected to the XI\/XO pins. The FREQSEL[1:0] pins are strapped to configure the internal PLL multiplier for the correct input frequency (11 = 40 MHz). The PLL generates the high-frequency clocks needed for the USB 3.0 PHY (5 GHz), the SATA PHY (1.5 or 3 GHz), and the Cortex-M3 core. The spread spectrum clock generation (SSCG) modulates the PLL output frequency slightly to reduce EMI peaks.\n\nPower Management: The TUSB9261 requires two supply voltages: 1.1 V (core, USB\/SATA PHY) and 3.3 V (I\/O, analog). The 1.1 V supply can be generated from the 3.3 V or 5 V input using an external LDO or switching regulator. The USB_VBUS pin detects USB bus power and can be used to control the external power supply. The device supports both VBUS-powered and externally-powered configurations.\n\nSPI EEPROM Interface: The SPI interface (SPI_SCLK, SPI_DATA_IN, SPI_DATA_OUT, SPI_CS0) connects to an external EEPROM (typically 128 KB or 256 KB) that stores the firmware image. At power-up, the boot ROM loads the firmware from the EEPROM into internal SRAM. Two additional chip selects (SPI_CS1, SPI_CS2) allow peripheral expansion. The SPI clock rate is configurable up to 25 MHz.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | VDD (1.1V)<\/td> | Power<\/td> | 1.1-V core power rail; 11 pins total (1, 12, 19, 32, 33, 41, 47, 49, 55, 61, 63); bypass each with 100 nF ceramic capacitor to GND; connect to external 1.1-V regulator output<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | PWM0<\/td> | Output (PD)<\/td> | Pulse-width modulation output; can drive activity\/status LEDs with configurable blink rate; open-drain output with internal pulldown (disabled by default); firmware controls blink speed; commonly used for HDD activity LED<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | PWM1<\/td> | Output (PD)<\/td> | Second PWM output for status LED; same characteristics as PWM0; can indicate power status or error conditions; firmware controls blink pattern<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | GRSTz<\/td> | Input (PU)<\/td> | Global power reset; active low with internal pullup; when asserted, all internal registers reset to defaults and the device is non-functional; must be deasserted for normal operation; connect 100 nF cap to GND for noise filtering; can be connected to system reset controller<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | GPIO8\/UART_RX<\/td> | I\/O (PU)<\/td> | Dual-function pin: GPIO or UART receiver; defaults to GPIO output; configure via firmware; UART RX used for debug serial console at 115200 baud; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | GPIO9\/UART_TX<\/td> | I\/O (PU)<\/td> | Dual-function pin: GPIO or UART transmitter; defaults to GPIO output; configure via firmware; UART TX used for debug serial console; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | VDD33<\/td> | Power<\/td> | 3.3-V digital I\/O power rail; 3 pins total (7, 24, 51); bypass each with 100 nF ceramic capacitor to GND<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8-16<\/td> | GPIO0-GPIO7<\/td> | I\/O (PD)<\/td> | General-purpose I\/O pins; configurable as inputs or outputs via firmware; internal pulldown resistors; GPIO0-4 on pins 8-11; GPIO5-7 on pins 14-16; commonly used for write-protect, power control, configuration strapping, and custom I\/O<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 17<\/td> | SPI_SCLK<\/td> | Output (PU)<\/td> | SPI clock output to external EEPROM and peripherals; up to 25 MHz; connect to EEPROM SCLK pin; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 18<\/td> | SPI_DATA_OUT<\/td> | Output (PU)<\/td> | SPI master data output; connect to EEPROM SI (Serial In) pin; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 20<\/td> | SPI_DATA_IN<\/td> | Input (PU)<\/td> | SPI master data input; connect to EEPROM SO (Serial Out) pin; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 21<\/td> | SPI_CS0<\/td> | Output (PU)<\/td> | Primary SPI chip select for firmware EEPROM; active low; connect to EEPROM CS pin; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 22<\/td> | SPI_CS1\/GPIO10<\/td> | I\/O (PU)<\/td> | SPI chip select for additional peripherals, or GPIO; configurable via firmware; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 23<\/td> | SPI_CS2\/GPIO11<\/td> | I\/O (PU)<\/td> | SPI chip select for additional peripherals, or GPIO; configurable via firmware; internal pullup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 25-29<\/td> | JTAG (TCK\/TDI\/TDO\/TMS\/TRSTz)<\/td> | I\/O<\/td> | JTAG interface for boundary scan (IEEE 1149.1\/1149.6) and firmware development; TCK(25), TDI(26), TDO(27), TMS(28), TRSTz(29); internal pullups on TDI\/TMS, pulldowns on TCK\/TRSTz<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 30-31<\/td> | FREQSEL[1:0]<\/td> | Input (PU)<\/td> | Frequency select strapping pins; configure PLL multiplier for input clock; 11 = 40 MHz (default); internal pullups; strap to appropriate logic level at PCB design time<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 35-36<\/td> | USB_DM\/USB_DP<\/td> | I\/O<\/td> | USB 2.0 High-Speed\/Full-Speed differential transceiver; USB_DM(35), USB_DP(36); connect to USB connector through ESD protection; route as differential pair with 90-Ohm impedance<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 38-39<\/td> | USB_R1\/USB_R1RTN<\/td> | I\/O<\/td> | Precision resistor reference for USB PHY calibration; connect a 10-kOhm plus or minus 1 percent resistor between R1(38) and R1RTN(39); this resistor sets the USB transceiver impedance and must be precision for signal quality<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 42-43<\/td> | USB_SSTXM\/USB_SSTXP<\/td> | Output<\/td> | SuperSpeed USB 3.0 transmit differential pair; negative(42) and positive(43); AC-coupled through 75 nF capacitors; route as differential pair with 90-Ohm impedance; keep away from SATA signals<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 45-46<\/td> | USB_SSRXM\/USB_SSRXP<\/td> | Input<\/td> | SuperSpeed USB 3.0 receive differential pair; negative(45) and positive(46); AC-coupled through 75 nF capacitors; route as differential pair with 90-Ohm impedance; keep away from SATA signals<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 50<\/td> | USB_VBUS<\/td> | Input<\/td> | USB bus power detection; connect to VBUS through resistor divider (if 5 V) or directly (if 3.3 V); used to detect USB connection and control power management; internal logic level is 3.3 V<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 52<\/td> | XI<\/td> | Input<\/td> | Crystal input; connect 40 MHz crystal with 1-MOhm feedback resistor to XO; alternatively, drive with 40 MHz external oscillator; when using crystal, connect load capacitors to VSSOSC<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 54<\/td> | XO<\/td> | Output<\/td> | Crystal output; if using external oscillator on XI, leave XO unconnected; when using crystal, 1-MOhm feedback resistor required between XI and XO<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 56-57<\/td> | SATA_TXM\/SATA_TXP<\/td> | Output<\/td> | SATA transmit differential pair; negative(56) and positive(57); AC-coupled through 10 nF capacitors; route as differential pair with 100-Ohm impedance; NOTE: default TI firmware swaps TXP\/TXM, verify with reference design<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 59-60<\/td> | SATA_RXM\/SATA_RXP<\/td> | Input<\/td> | SATA receive differential pair; negative(59) and positive(60); AC-coupled through 10 nF capacitors; route as differential pair with 100-Ohm impedance<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|