The TPS54627DDAR from Texas Instruments is a 4.5-V to 18-V input, 6-A synchronous step-down converter with integrated MOSFETs in an 8-pin SO PowerPAD (DDA) package (4.89 x 3.90 mm). Key specifications: input voltage range 4.5 V to 18 V; output voltage range 0.76 V to 5.5 V; maximum output current 6 A; D-CAP2 mode control for fast transient response with no external compensation; compatible with ceramic output capacitors; integrated NMOS FETs with 36 mOhm high-side and 28 mOhm low-side RDSON; fixed switching frequency 650 kHz; high initial bandgap reference accuracy; adjustable soft start; prebiased soft start; cycle-by-cycle overcurrent limiting; output discharge control; OVP, UVP, UVLO, and TSD protections; quiescent current 950 uA typical; shutdown current less than 10 uA; maximum duty cycle 65 percent. The DDA package (SO PowerPAD-8) has a footprint of 829.4 mm squared (4.9 x 6 mm). The DDAR suffix denotes tape and reel packaging. A newer version, TPS566238, is available with higher efficiency in a smaller package. RoHS compliant.<\/p>","protected":false},"excerpt":{"rendered":"
The TPS54627DDAR from Texas Instruments is a 4.5-V to 18-V input, 6-A synchronous step-down converter with integrated MOSFETs in an 8-pin SO PowerPAD (DDA) package (4.89 x 3.90 mm). Key specifications: input voltage range 4.5 V to 18 V; output voltage range 0.76 V to 5.5 V; maximum output current 6 A; D-CAP2 mode control […]<\/p>\n","protected":false},"author":2,"featured_media":2910,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[14,13],"tags":[],"chip_brand":[138],"class_list":["post-1943","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-clock-timing-ics","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"4.5-18V 6A sync buck converter, D-CAP2, 650kHz, integrated FETs 36\/28mOhm, no ext comp, adj SS, SO-8 PowerPAD, -40~85C, tape&reel","date_code":"","package_case":"SO PowerPAD-8 (DDA) (4.89 x 3.90 mm)","in_stock":8000,"datasheet":"https:\/\/www.ti.com\/product\/TPS54627","price":"$2.10 (1K+ pcs)","product_introduction":"The TPS54627DDAR from Texas Instruments is a fully integrated synchronous buck converter that combines the controller, high-side and low-side MOSFETs, and compensation circuitry in a single 8-pin SO PowerPAD package. With 6 A of output current and a 4.5-18 V input range, it addresses the most common point-of-load conversion requirements in digital TV, set-top box, networking, and industrial applications.\n\nAs an integrated converter (not a controller), the TPS54627 includes the power MOSFETs on-chip, eliminating the need for external MOSFET selection, gate drive design, and current-sense circuitry. This dramatically simplifies the design process and reduces the solution footprint compared to a controller-plus-external-FET approach. The integrated FETs have RDSON values of 36 mOhm (high-side) and 28 mOhm (low-side), optimized for lower duty-cycle applications where the low-side FET carries current for a larger portion of the switching period.\n\nThe D-CAP2 control mode, shared with other TPS family devices, provides fast transient response without external compensation components. The internal ripple injection circuit ensures stable operation with ceramic output capacitors, which are preferred for their low ESR, long lifetime, and small size. The 650 kHz fixed switching frequency provides a good balance between efficiency and inductor\/capacitor size for most applications.\n\nThe adjustable soft-start feature allows the designer to control the output voltage ramp-up rate by selecting an external capacitor on the SS pin. This is important for applications with strict power sequencing requirements or where inrush current must be limited. The prebiased soft-start capability ensures that the converter does not sink current from a precharged output, preventing output voltage undershoot during startup.\n\nThe SO PowerPAD (DDA) package provides excellent thermal performance through an exposed thermal pad that solders directly to the PCB ground plane. This thermal path keeps the junction temperature within safe limits even at full 6-A load with natural convection cooling, provided the PCB has adequate copper area connected to the PowerPAD.\n\nThe DDAR suffix indicates tape and reel packaging (DDA = SO PowerPAD-8, R = tape and reel), suitable for automated SMT assembly.\n\nTI recommends the TPS566238 as a newer alternative with higher efficiency in a smaller package for new designs, though the TPS54627 remains in active production and is widely stocked by distributors.","working_principle":"The TPS54627DDAR operates as a fully integrated synchronous buck converter using D-CAP2 mode control with integrated power MOSFETs.\n\nD-CAP2 Mode Control: The control loop uses the D-CAP2 architecture where the output voltage (sensed at the VFB pin through a resistor divider) is compared to an internal 0.760-V reference. The adaptive on-time controller generates PWM pulses whose duration is proportional to VOUT\/VIN, maintaining a relatively constant 650 kHz switching frequency. The internal ripple injection circuit adds a synthetic ripple to the VFB signal, ensuring stable operation even with very-low-ESR ceramic output capacitors. No external Type-II or Type-III compensation network is required.\n\nIntegrated Power MOSFETs: The high-side NMOS (36 mOhm RDSON) and low-side NMOS (28 mOhm RDSON) are integrated on the same die as the controller. The SW pin is the switch node connecting the two MOSFETs. The bootstrap supply for the high-side driver is provided through an internal diode from VREG5 to VBST, with a 0.1-uF external capacitor between VBST and SW. The adaptive dead-time control prevents shoot-through current by ensuring both MOSFETs are never on simultaneously.\n\n5-V Internal Regulator: The VREG5 pin provides a 5.5-V output from an internal linear regulator that drops VIN. This supplies the gate drive circuitry for both MOSFETs. A 1-uF bypass capacitor to GND is required. VREG5 is active only when EN is high, reducing quiescent current in shutdown.\n\nSoft Start: An external capacitor on the SS pin controls the soft-start time. The SS pin sources 2.3 uA to charge the external capacitor, and the reference voltage tracks the SS pin voltage during startup. The soft-start time is calculated as tSS = CSS x VREF \/ ISS = CSS x 0.76 \/ 2.3 uA. For a 22-nF capacitor, tSS is approximately 7.3 ms. During prebiased startup, the converter does not sink current from the output.\n\nOvercurrent Protection: The cycle-by-cycle overcurrent limit senses the peak inductor current through the low-side MOSFET RDSON during the off-time. If the current exceeds the limit (approximately 8 A typical), the high-side MOSFET is prevented from turning on in the next cycle. This provides fast protection against overloads and short circuits.\n\nOutput Discharge: When the converter is disabled (EN low or UVLO), the internal discharge MOSFET connects the output to GND through a 200-Ohm resistor, discharging the output capacitors. This ensures the output voltage drops to zero quickly when the converter is turned off, which is important for proper power sequencing.\n\nOvervoltage Protection: If the output exceeds approximately 112 percent of the target voltage, the high-side MOSFET is turned off and the low-side MOSFET is turned on to discharge the output. This protects downstream circuitry from overvoltage damage.\n\nThermal Shutdown: The internal thermal shutdown circuit disables the converter when the junction temperature exceeds approximately 160 degrees C. The converter automatically restarts when the junction temperature drops by approximately 20 degrees C.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | EN<\/td> | Input<\/td> | Enable input; active high; pull above 1.26 V to enable the converter; pull below 0.62 V to disable and enter shutdown mode (less than 10 uA quiescent current); can be connected to VIN through a resistor divider for adjustable UVLO threshold, or driven by a logic signal; internal pull-down resistor ensures off if EN is floating<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | VFB<\/td> | Input<\/td> | Converter feedback input; connect to the output voltage through a resistor divider; internal reference voltage 0.760 V; output voltage set by VOUT = 0.760 x (R1+R2)\/R2; also serves as input for OVP and UVP comparators; route away from noisy switch-node and inductor traces for clean feedback signal<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | VREG5<\/td> | Output<\/td> | 5.5-V output of the internal linear regulator; supplies the gate driver circuitry; bypass to GND with a 1-uF ceramic capacitor; VREG5 is active only when EN is high; do not connect external loads that draw more than 5 mA; the regulator input is from VIN, providing the 5.5-V gate drive even when VIN is as low as 4.5 V<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | SS<\/td> | Input<\/td> | Soft-start control; connect an external capacitor from SS to GND to set the soft-start time; the pin sources 2.3 uA to charge the capacitor; the reference voltage tracks the SS pin voltage during startup; tSS = CSS x 0.76 \/ 2.3 uA; leaving SS unconnected results in minimum soft-start time (approximately 0.5 ms); the SS pin is also used for output discharge when EN is low<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | GND<\/td> | Ground<\/td> | Ground; power ground return for the switching circuit and control circuitry; connect sensitive SS and VFB returns to GND at a single point to minimize ground-loop noise; connect the PowerPAD thermally and electrically to the PCB ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | SW<\/td> | Output<\/td> | Switch node; internal connection between the high-side and low-side MOSFETs; connect the output inductor to this pin; the SW node has high dv\/dt switching transients; keep the inductor connection as short as possible; the SW pin also provides the bootstrap return for the high-side driver<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | VBST<\/td> | Output<\/td> | Bootstrap supply input for the high-side MOSFET gate driver; connect a 0.1-uF ceramic capacitor between VBST and SW; the bootstrap capacitor is charged from VREG5 through an internal diode when SW is low (low-side MOSFET on); the bootstrap voltage provides the gate drive for the high-side MOSFET<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | VIN<\/td> | Input<\/td> | Input voltage supply pin; accepts 4.5 V to 18 V; bypass to GND with a minimum 10-uF ceramic capacitor placed close to the pin; VIN powers both the internal circuitry (through the VREG5 regulator) and the high-side MOSFET drain; connect directly to the input power rail with minimal trace impedance<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Pad<\/td> | PowerPAD<\/td> | Ground<\/td> | Thermal pad of the SO PowerPAD package; must be soldered to the PCB ground plane for proper thermal dissipation; electrical connection to GND; the thermal resistance from junction to case depends heavily on the copper area connected to this pad; recommended minimum 2 sq in of 2-oz copper for 6-A operation<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|