The DRV8833PWPR from Texas Instruments is a dual H-bridge current-controlled motor driver in a 16-pin HTSSOP (PWP) package with PowerPAD (5.00 x 6.40 mm). It can drive two DC brush motors or one bipolar stepper motor. Motor supply voltage: 2.7V to 10.8V. Low MOSFET on-resistance: HS+LS = 360mOhm typical at 5V\/25C. Output current per H-bridge: 1.5A RMS \/ 2A peak (PWP package). Outputs can be paralleled for 3A RMS \/ 4A peak operation. PWM winding current regulation and current limiting via external sense resistors on AISEN\/BISEN pins. Simple PWM interface: 4 logic inputs (AIN1, AIN2, BIN1, BIN2) control motor direction and brake. nSLEEP pin for low-power sleep mode (1.6uA typical at 5V). nFAULT open-drain output for overcurrent, short-circuit, UVLO, and thermal shutdown fault reporting. Internal charge pump for high-side gate drive (0.01uF cap between VCP and VM). VINT internal 3.3V regulator bypass (2.2uF cap to GND). Both fast and slow decay modes supported. Operating temperature: -40C to +85C. Active product, RoHS compliant, EAR99.<\/p>","protected":false},"excerpt":{"rendered":"
The DRV8833PWPR from Texas Instruments is a dual H-bridge current-controlled motor driver in a 16-pin HTSSOP (PWP) package with PowerPAD (5.00 x 6.40 mm). It can drive two DC brush motors or one bipolar stepper motor. Motor supply voltage: 2.7V to 10.8V. Low MOSFET on-resistance: HS+LS = 360mOhm typical at 5V\/25C. Output current per H-bridge: […]<\/p>\n","protected":false},"author":2,"featured_media":2841,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[],"chip_brand":[138],"class_list":["post-1924","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual H-bridge motor driver, 2.7-10.8V, 1.5A RMS\/2A peak, 360mOhm, PWM current regulation, parallel mode 3A, HTSSOP-16, Active","date_code":"","package_case":"HTSSOP-16 (PWP) with PowerPAD (5.00 x 6.40 x 1.05 mm)","in_stock":2100,"datasheet":"https:\/\/www.ti.com\/product\/DRV8833","price":"$1.18 (1K+ pcs)","product_introduction":"The DRV8833PWPR from Texas Instruments is a versatile dual H-bridge motor driver that provides an efficient and compact solution for driving two DC brush motors or one bipolar stepper motor. Housed in a thermally enhanced 16-pin HTSSOP package with PowerPAD, it delivers up to 1.5A RMS per H-bridge with a low MOSFET on-resistance of 360mOhm (HS+LS combined), minimizing power dissipation and maximizing efficiency.\n\nThe DRV8833 is one of TI's most popular motor driver ICs, widely used in battery-powered toys, POS printers, security cameras, office automation equipment, gaming machines, and robotics. Its combination of wide supply range (2.7V to 10.8V), moderate current capability (1.5A RMS per bridge), PWM current regulation, and comprehensive protection features makes it a go-to choice for many low-voltage motor drive applications.\n\nThe device features two independent H-bridges, each consisting of N-channel power MOSFETs in a standard H-bridge configuration. Each H-bridge can independently drive a DC motor bidirectionally, or the two H-bridges can work together to drive a single bipolar stepper motor. The outputs can also be paralleled (AOUT1+BOUT1, AOUT2+BOUT2) to deliver 3A RMS and 4A peak to a single motor, which is useful for driving higher-current loads with a single device.\n\nThe PWM current regulation feature uses external sense resistors connected between the AISEN\/BISEN pins and GND to set the current regulation threshold. The internal 200mV reference comparator monitors the voltage across the sense resistor and chops the current when it exceeds the threshold. This allows precise control of motor winding current, which is essential for stepper motor applications where consistent torque and microstepping accuracy depend on accurate current setting. The current trip point is calculated as: I_trip = 0.2V \/ R_sense. For a 0.2Ohm sense resistor, I_trip = 1A.\n\nThe simple 4-pin PWM control interface (AIN1, AIN2, BIN1, BIN2) requires no serial communication or register programming. Each pair of inputs directly controls the state of the corresponding H-bridge outputs. This makes the DRV8833 easy to interface with any microcontroller using just 4 GPIO pins. Speed control is achieved by applying PWM signals to the input pins.\n\nThe HTSSOP-16 (PWP) package with PowerPAD provides the best thermal performance among the available DRV8833 package options. The PowerPAD (exposed thermal pad on the bottom of the package) must be soldered to the PCB ground plane for proper heat dissipation. The junction-to-board thermal resistance is 28.8C\/W for the PWP package, compared to 44.7C\/W for the WQFN (RTE) package, allowing higher continuous current in the same ambient temperature.\n\nThe PWP package also offers the highest current rating of 1.5A RMS per bridge (compared to 0.6A RMS for the WQFN package and 0.5A RMS for the TSSOP PW package). The 2A peak current per bridge can handle motor startup transients and brief overloads. When outputs are paralleled, the combined 3A RMS and 4A peak capability can drive substantial loads.\n\nThe DRV8833PWPR is the tape-and-reel version (2000 units per reel), while the DRV8833PWP is the tube version (90 units per tube). Both have identical electrical characteristics.","working_principle":"The DRV8833PWPR operates as a dual H-bridge motor driver with PWM current regulation capability.\n\nH-Bridge Operation: Each H-bridge consists of four N-channel power MOSFETs arranged in a bridge configuration. N-channel MOSFETs are used for both high-side and low-side positions, providing lower on-resistance than P-channel alternatives. The combined HS+LS on-resistance of 360mOhm results in minimal voltage drop and power dissipation at rated current. At 1.5A, the voltage drop across the MOSFETs is approximately 540mV, and the power dissipation per bridge is approximately 810mW.\n\nCharge Pump: Since N-channel MOSFETs are used for the high-side switches, a gate voltage above the source (output) voltage is needed to turn them on. The internal charge pump generates this elevated gate drive voltage. A 0.01uF capacitor connected between VCP and VM stores the charge pump output. The charge pump operates automatically and requires no external timing components. It provides sufficient gate drive across the full 2.7V to 10.8V supply range.\n\nPWM Current Regulation: When current regulation is enabled (sense resistors connected to AISEN\/BISEN), the driver monitors the motor current through the sense resistors. When the current exceeds the threshold (I_trip = 0.2V \/ R_sense), the driver enters a decay mode for a fixed off-time period. The DRV8833 supports both fast decay (outputs high-impedance, current flows through body diodes) and slow decay (outputs shorted, current recirculates through low-side MOSFETs). Fast decay provides faster current reduction but may cause voltage spikes; slow decay provides smoother current waveform but slower reduction. The decay mode is determined by the state of the input pins during the off-time.\n\nLogic Control Truth Table: xIN1=0, xIN2=0: Coast (both outputs high-Z, fast decay). xIN1=1, xIN2=0: Forward (xOUT1=HIGH, xOUT2=LOW). xIN1=0, xIN2=1: Reverse (xOUT1=LOW, xOUT2=HIGH). xIN1=1, xIN2=1: Brake (both outputs LOW, slow decay). PWM speed control is achieved by toggling between the active state (forward or reverse) and the coast or brake state at a frequency above the motor's mechanical response bandwidth (typically 10kHz to 50kHz).\n\nParalleling Outputs: For higher-current applications, the two H-bridges can be paralleled by connecting AOUT1 to BOUT1 and AOUT2 to BOUT2, and driving AIN1=BIN1 and AIN2=BIN2 simultaneously. This effectively doubles the current capacity to 3A RMS and 4A peak. The sense resistors should also be paralleled (or a single sense resistor with half the resistance should be used) to maintain the same current trip threshold.\n\nSleep Mode: The nSLEEP pin provides a low-power sleep mode. When driven LOW, all internal circuitry including the charge pump is disabled, and the outputs enter a high-impedance state. The supply current drops to 1.6uA typical (5V), preserving battery life in always-on applications. An internal pulldown resistor (500kOhm) ensures the device enters sleep mode if the nSLEEP pin is left floating. Wake-up time from sleep is approximately 155us, which includes charge pump startup and regulator stabilization.\n\nProtection Circuits: Overcurrent protection (OCP) limits current through each MOSFET to a safe level (approximately 3-4A) by disabling the affected bridge. Thermal shutdown (TSD) disables both bridges when the junction temperature exceeds approximately 150C. Undervoltage lockout (UVLO) disables the outputs when VM drops below approximately 2.5V. Short-circuit protection detects output-to-supply and output-to-ground faults. All fault conditions are reported through the nFAULT open-drain output, which requires an external pull-up resistor.","pin_description":"
| Pin (PWP)<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | nSLEEP<\/td> | Input<\/td> | Sleep mode input; logic HIGH = normal operation; logic LOW = low-power sleep mode (1.6uA typical); internal pulldown (500kOhm) ensures sleep if pin floats; wake-up time ~155us; toggling nSLEEP resets all internal logic<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | AOUT1<\/td> | Output<\/td> | Bridge A output 1; connect to motor winding A; positive current direction is AOUT1 to AOUT2; can be paralleled with BOUT1 for higher current<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | AISEN<\/td> | I\/O<\/td> | Bridge A current sense; connect external sense resistor to GND for PWM current regulation (I_trip = 0.2V \/ R_sense); connect directly to GND if current regulation is not needed; sense resistor should be rated for motor current with adequate power dissipation<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | AOUT2<\/td> | Output<\/td> | Bridge A output 2; connect to motor winding A; can be paralleled with BOUT2<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | BOUT2<\/td> | Output<\/td> | Bridge B output 2; connect to motor winding B<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | BISEN<\/td> | I\/O<\/td> | Bridge B current sense; connect external sense resistor to GND for PWM current regulation; connect directly to GND if not needed<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | BOUT1<\/td> | Output<\/td> | Bridge B output 1; connect to motor winding B; positive current direction is BOUT1 to BOUT2<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | nFAULT<\/td> | Open-Drain Output<\/td> | Fault indicator; active-low open-drain; asserts during overcurrent, short-circuit, UVLO, or overtemperature; requires external pull-up resistor (10kOhm typical) to logic supply; returns high-impedance when fault clears<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | BIN1<\/td> | Input<\/td> | Bridge B input 1; logic input controls BOUT1 state; internal pulldown (100-150kOhm); compatible with 3.3V and 5V logic; VIH min = 2.0V, VIL max = 0.7V<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | BIN2<\/td> | Input<\/td> | Bridge B input 2; logic input controls BOUT2 state; internal pulldown<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 11<\/td> | VCP<\/td> | I\/O<\/td> | Charge pump output for high-side gate drive; connect 0.01uF ceramic capacitor (16V minimum, X7R) between VCP and VM; charge pump operates automatically; no external timing components needed<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 12<\/td> | VM<\/td> | Power<\/td> | Motor power supply; 2.7V to 10.8V operating range; bypass to GND with 10uF (minimum) ceramic capacitor rated for maximum VM; input current = motor current + quiescent current<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 13<\/td> | GND<\/td> | Ground<\/td> | Device ground; PowerPAD must also be connected to GND plane for thermal management; all load current returns through GND and PowerPAD<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 14<\/td> | VINT<\/td> | Power<\/td> | Internal 3.3V regulator output; bypass to GND with 2.2uF, 6.3V ceramic capacitor; powers internal logic and control circuitry; do not use to power external loads<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 15<\/td> | AIN2<\/td> | Input<\/td> | Bridge A input 2; logic input controls AOUT2 state; internal pulldown<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 16<\/td> | AIN1<\/td> | Input<\/td> | Bridge A input 1; logic input controls AOUT1 state; internal pulldown<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| PPAD<\/td> | PowerPAD<\/td> | Ground<\/td> | Exposed thermal pad; must be soldered to PCB ground plane; electrically connected to GND internally; critical for thermal performance (RthetaJC(bottom) = 4.8C\/W)<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
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